LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 36. Auto-Negotiation and Fast Link Pulse Timing
Clock Pulse
Data Pulse
Clock Pulse
TPFOP
t1
t1
t3
t2
Figure 37. Fast Link Pulse Timing
FLP Burst
FLP Burst
TPFOP
t4
t5
Table 37. Auto-Negotiation and Fast Link Pulse Timing Parameters
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Clock/Data pulse width
Clock pulse to Data pulse
Clock pulse to Clock pulse
FLP burst width
t1
t2
t3
t4
t5
–
–
55.5
123
–
100
–
–
63.8
127
–
ns
µs
–
–
–
–
–
–
–
µs
2
ms
ms
ea
FLP burst to FLP burst
Clock/Data pulses per burst
8
12
–
24
17
33
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
68
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
INTEL [ INTEL ]
