LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 12. BSR Mode of Operation
Mode
Description
1
2
3
4
Capture
Shift
Update
System Function
Table 13. Supported JTAG Instructions
Name
EXTEST
Code
Description
External Test
Mode
Data Register
BSR
1111 1111 1110 1000
1111 1111 1111 1110
1111 1111 1111 1000
1111 1111 1100 1111
1111 1111 1110 1111
1111 1111 1111 1111
Test
IDCODE
SAMPLE
HIGHZ
ID Code Inspection
Sample Boundary
Force Float
Normal
Normal
Normal
Test
ID REG
BSR
Bypass
Bypass
Bypass
CLAMP
BYPASS
Control Boundary to 1/0
Bypass Scan
Normal
Table 14. Device ID Register
31:28
27:12
11:8
7:1
0
Version2
Part ID (hex)
Jedec Continuation Characters
JEDEC ID1
Reserved
XXXX
03CB
0000
111 1110
1
1. The JEDEC IS is an 8-bit identifier. The MSB is for parity and is ignored. Intel’s JEDEC ID is FE
(1111 1110), which becomes 111 1110.
2. See the LXT971A/972A Specification Update (document number 249354) for the current version of the
Jedec continuation characters.
Datasheet
47
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
INTEL [ INTEL ]
