LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
1.0
Pin Assignments
Figure 2. LXT971A 64-Ball PBGA Assignments
1
2
3
4
5
6
7
8
A
B
C
D
E
F
MDINT
CRS
TXD3
TXD0
RX_ER VCCD RX_DV
RXD0
A
B
C
D
E
F
REF
RX_
COL
TXD2
GND
TX_EN TX_ER
N/C
N/C
RXD1
RXD2
MDIO
CLK/XI
CLK
TX_
TXD1
XO
Tx
RESET
Tx
GND
CLK
MDDIS
GND
GND
GND
GND
VCCA
VCCIO
VCCIO
TDI
RXD3
N/C
SLEW0 SLEW1
LED/
PWR
DWN
ADDR0 ADDR1
MDC
CFG1
LED/
LED/
ADDR3 ADDR2
ADDR4 SD/TP
GND
TMS
TCK
CFG2
CFG3
G
H
VCCA
TDO
GND
GND
G
H
RBIAS TPFOP TPFON TPFIP
TPFIN
5
TRST
6
SLEEP PAUSE
1
2
3
4
7
8
12
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002