LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 1. LXT971A Block Diagram
RESET
ADDR<4:0>
MDIO
MDC
MDINT
MDDIS
TX_EN
TX PCS
TXD<3:0>
TX_ER
TX_CLK
Parallel/Serial
Converter
Management /
Mode Select
Logic
Power Supply
Register Set
Clock
Generator
Manchester
10
Encoder
Scrambler
100
& Encoder
Auto
Negotiation
Register
Set
VCC
GND
PWRDWN
REFCLK
TxSLEW<1:0>
OSP
™
Pulse
Shaper
TP
Driver
+
-
+
-
JTAG
5
TP/Fiber
Out
TPFOP
TPFON
ECL
Driver
LED/CFG<3:1>
Collision
Detect
OSP
™
Clock
Generator
Manchester
Decoder
Decoder &
Descrambler
Media
Select
Adaptive EQ with
Baseline Wander
Cancellation
100TX
COL
+
-
+
100FX
TP/Fiber In
TDIO
TMS
TCK
TRST
RX_CLK
RXD<3:0>
RX PCS
RXDV
CRS
RX_ER
Carrier Sense
Data Valid
Error Detect
Serial-to-
Parallel
Converter
10
100
TPFIP
TPFIN
SD/TP
OSP
™
Slicer
-
+
10BT
-
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
11
INTEL [ INTEL CORPORATION ]
