LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 1. LXT971A Block Diagram
RESET
VCC
Power Supply
GND
Management /
Mode Select
Logic
ADDR<4:0>
MDIO
PWRDWN
Register Set
REFCLK
Clock
MDC
Generator
MDINT
TxSLEW<1:0>
MDDIS
+
Manchester
Encoder
10
TX_EN
TXD<3:0>
TX_ER
TP
OSP™
Driver
TPFOP
TPFON
Pulse
Parallel/Serial
Converter
Scrambler
& Encoder
-
+
100
TP/Fiber
Out
Shaper
TX_CLK
ECL
Auto
Driver
Negotiation
-
TDIO
TMS
TCK
Register
Set
5
LED/CFG<3:1>
COL
JTAG
OSP™
TRST
Adaptive EQ with
Baseline Wander
Cancellation
+
Collision
Detect
Media
Select
Clock
100TX
100FX
10BT
Generator
-
RX_CLK
RXD<3:0>
RXDV
+
TPFIP
TPFIN
SD/TP
Manchester
Serial-to-
Parallel
TP/Fiber In
10
Decoder
OSP™
Slicer
-
Converter
Decoder &
Carrier Sense
100
CRS
Descrambler
+
Data Valid
Error Detect
RX_ER
-
Datasheet
11
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
INTEL [ INTEL ]
