Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 39.
Device Clock Timings (Oscillator Reference) (Sheet 2 of 2)
Symbol
Parameter
Load capacitance
Min.
Nom.
Max.
Units
Notes
C1
C2
pF
pF
%
2
2
3
Load capacitance
Duty cycle
TDC
35
50
65
Notes:
1.
This value could be an oscillator input or a series resonant frequency from a crystal. If used as an
oscillator input, tie to the crystal input pin and leave the crystal output pin disconnected.
Use the component values recommended by the crystal manufacturer.
2.
3.
4.
This parameter applies when driving the clock input with an oscillator.
Where the IXP42X product line or IXC1100 control plane processor is configured with an input
reference-clock, the slew rate should never be faster than 2.5 V/nS to ensure proper PLL operation.
To help ensure proper PLL operation at the slower slew rate, the VIH and VIL voltage levels need to
be within the specified range at an input clock frequency of 33.33 MHz.
.
Table 40.
Device Clock Timings (Crystal Reference)
Symbol
Parameter
Input-high voltage
Min.
Nom.
Max.
Units
Notes
VIH
VIL
1.9
V
V
Input-low voltage
1.6
Clock frequency for IXP42X product
TFREQUENCY line and IXC1100 control plane
processors crystal or oscillator.
33.33
MHz
1, 4
UFREQUENCY Clock tolerance over -40º C to 85º C.
-50
50
60
ppm
ESR
Equivalent Series Resistance
Ω
Pin capacitance of IXP42X product line
and IXC1100 control plane processors’
inputs.
CIN
5
3
pF
pF
CSHUNT is a crystal parameter
sometimes referred to as the holder
capacitance.
CSHUNT
2
4
C1
C2
Load capacitance
Load capacitance
Duty cycle
pF
pF
%
2
2
3
TDC
35
50
65
Notes:
IMPORTANT NOTE: Please refer to the product specification update regarding new crystal specifications.
1.
This value could be an oscillator input or a series resonant frequency from a crystal. If used as an
oscillator input, tie to the crystal input pin and leave the crystal output pin disconnected.
Use the component values recommended by the crystal manufacturer.
2.
3.
4.
This parameter applies when driving the clock input with an oscillator.
Where the IXP42X product line or IXC1100 control plane processor is configured with an input
reference-clock, the slew rate should never be faster than 2.5 V/nS to ensure proper PLL operation.
To help ensure proper PLL operation at the slower slew rate, the VIH and VIL voltage levels need to
be within the specified range at an input clock frequency of 33.33 MHz.
March 2005
92
Datasheet
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
