Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.4.14
Reset DC Parameters
Table 38.
PWRON_RESET_N DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
The input voltage
must not exceed
1.3V or long-term
reliability may be
adversely affected.
VIH
Input-high voltage
1.0
1.3
V
VIL
IIL
Input-low voltage
0.3
10
1
V
0 < VIN
1.3V
<
Input leakage current
Input Capacitance
-500
µA
pF
CIN
Simulated results.
5.5
AC Specifications
5.5.1
Clock Signal Timings
Processor Clock Timings
5.5.1.1
Crystal oscillators require that good system-level design practices be followed for reliable start-up
and oscillation. Please refer to the Intel® IXP42X Product Line of Network Processors and
IXC1100 Control Plane Processor Product Line: Crystal Design Considerations Application Note
(Document Number 305588), and contact Intel for the recommended Intel® IXP42X Product Line
of Network Processors and IXC1100 Control Plane Processor part number optimized for use with
crystal oscillators.
Table 39.
Device Clock Timings (Oscillator Reference) (Sheet 1 of 2)
Symbol
Parameter
Input-high voltage
Min.
Nom.
Max.
Units
Notes
VIH
VIL
2.0
V
V
Input-low voltage
0.8
Clock frequency for IXP42X product line
TFREQUENCY and IXC1100 control plane processors
crystal or oscillator.
33.33
MHz
1, 4
UFREQUENCY Clock tolerance over -40º C to 85º C.
-50
2
50
4
ppm
pF
Pin capacitance of IXP42X product line and
IXC1100 control plane processors’ inputs.
CIN
5
3
CSHUNT is a crystal parameter sometimes
CSHUNT
pF
referred to as the holder capacitance.
Notes:
1.
This value could be an oscillator input or a series resonant frequency from a crystal. If used as an
oscillator input, tie to the crystal input pin and leave the crystal output pin disconnected.
Use the component values recommended by the crystal manufacturer.
2.
3.
4.
This parameter applies when driving the clock input with an oscillator.
Where the IXP42X product line or IXC1100 control plane processor is configured with an input
reference-clock, the slew rate should never be faster than 2.5 V/nS to ensure proper PLL operation.
To help ensure proper PLL operation at the slower slew rate, the VIH and VIL voltage levels need to
be within the specified range at an input clock frequency of 33.33 MHz.
Datasheet
March 2005
Document Number: 252479, Revision: 005
91
INTEL [ INTEL ]
