Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 23.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 3 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
J1
J2
J3
J4
J5
J6
PCI_CLKIN
VCCP
K1
K2
K3
K4
K5
K6
PCI_CBE_N[2]
VSS
L1
L2
L3
L4
L5
PCI_DEVSEL_N
VCCP
M1
M2
M3
M4
M5
PCI_CBE_N[1]
PCI_PAR
VSS
VSS
PCI_AD[17]
VCCP
PCI_STOP_N
VCC
PCI_AD[22]
VSS
PCI_IRDY_N
VCCP
PCI_AD[19]
VCC
PCI_FRAME_N
PCI_AD[29]
L11
L12
L13
L14
L15
L16
VSS
VSS
VSS
VSS
VSS
VSS
M11
M12
M13
M14
M15
M16
VSS
VSS
VSS
VSS
VSS
VSS
J21
J22
EX_ADDR[8]
EX_ADDR[16]
VCC
K21
K22
K23
K24
K25
K26
VCC
VSS
L22
L23
L24
L25
L26
VCCP
VCC
M22
M23
M24
M25
M26
EX_CS_N[5]
EX_CLK
J23
EX_CS_N[0]
EX_CS_N[3]
VCCP
J24
EX_ADDR[23]
EX_CS_N[2]
EX_CS_N[4]
EX_CS_N[6]
EX_DATA[0]
EX_DATA[1]
EX_DATA[2]
VSS
J25
J26
EX_CS_N[7]
EX_DATA[3]
Note:
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 33.
Datasheet
March 2005
69
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
