Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 23.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 7 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AE1 ETH_RXDATA0[3] AF1
ETH_RXDATA0[2]
ETH_MDIO
(Reserved)
N/C
AE2
AE3
VCCP
ETH_COL0
N/C
AF2
AF3
AE4
AF4
AE5
VCCP
N/C
AF5
N/C
AE6
AF6
N/C
AE7
VSS
AF7
N/C
AE8
N/C
AF8
VSSOSC
OSC_IN
AE9
VCCP
VCCPLL1
VSS
AF9
AE10
AE11
AE12
AE13
AF10
AF11
AF12
AF13
VSSOSCP
OSC_OUT
VCCOSC
BYPASS_CLK
VCCPLL2
VCCP
AE14 UTP_OP_DATA[5] AF14 UTP_OP_DATA[6]
AE15
AE16
AE17
VSS
UTP_OP_FCO
VCCP
AF15 UTP_OP_DATA[3]
AF16 UTP_OP_DATA[0]
AF17
UTP_OP_CLK
AE18 UTP_OP_ADDR[2] AF18 UTP_OP_ADDR[4]
AE19 VSS AF19 UTP_OP_ADDR[0]
AE20 UTP_IP_DATA[4] AF20
UTP_IP_DATA[5]
UTP_IP_DATA[3]
UTP_IP_DATA[0]
AE21
AE22
AE23
AE24
AE25
AE26
Note:
VCCP
UTP_IP_FCO
VCCP
AF21
AF22
AF23 UTP_IP_ADDR[3]
AF24 UTP_IP_ADDR[2]
JTG_TDI
VCCP
AF25
AF26
JTG_TMS
JTG_TCK
HIGHZ_N
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 33.
Datasheet
March 2005
73
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
