Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 22.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 7 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AE1 ETH_RXDATA0[3] AF1
ETH_RXDATA0[2]
ETH_MDIO
(Reserved)
ETH_TXDATA1[3]
ETH_TXCLK1
ETH_RXDATA1[0]
ETH_CRS1
VSSOSC
OSC_IN
VSSOSCP
OSC_OUT
VCCOSC
BYPASS_CLK
N/C
AE2
AE3
VCCP
ETH_COL0
ETH_TXEN1
VCCP
AF2
AF3
AE4
AF4
AE5
AF5
AE6
ETH_RXDV1
VSS
AF6
AE7
AF7
AE8
ETH_COL1
VCCP
AF8
AE9
AF9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
Note:
VCCPLL1
VSS
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
VCCPLL2
VCCP
N/C
VSS
N/C
N/C
N/C
VCCP
N/C
N/C
N/C
VSS
N/C
N/C
N/C
VCCP
N/C
N/C
N/C
VCCP
N/C
JTG_TDI
VCCP
N/C
JTG_TMS
JTG_TCK
HIGHZ_N
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 33.
March 2005
66
Datasheet
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
