Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 23.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 5 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
U1
U2
U3
U4
U5
U6
PCI_AD[8]
VCCP
V1
V2
V3
V4
V5
V6
PCI_AD[5]
VSS
W1
W2
PCI_AD[1]
VCCP
Y1
Y2
HSS_TXCLK0
HSS_RXCLK0
HSS_TXFRAME1
VCC
PCI_AD[0]
PCI_AD[7]
HSS_TXDATA0
VCC
PCI_AD[3]
VCC
W3 HSS_RXFRAME0 Y3
W4
W5
VSS
Y4
Y5
HSS_TXFRAME0
VSS
HSS_TXCLK1
VCCP
W6 HSS_RXFRAME1 Y6
ETH_TXEN0
U21
U22
U23
U24
U25
U26
Note:
VCC
V21
V22
V23
V24
V25
V26
GPIO[6]
GPIO[9]
W21
W22
W23
W24
W25
W26
GPIO[1]
VCCP
Y21
Y22
Y23
Y24
Y25
Y26
RXDATA1
GPIO[0]
VCC
GPIO[14]
EX_RDY_N[1]
EX_RDY_N[2]
GPIO[15]
VCC
GPIO[8]
VSS
GPIO[13]
VCCP
GPIO[5]
VCCP
GPIO[11]
GPIO[12]
EX_DATA[15]
EX_RDY_N[3]
GPIO[10]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 33.
Datasheet
March 2005
71
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
