Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 55.
Intel Simplex Mode Values
Symbol
Parameter
Min. Max. Units
Notes
Taddr2valcs
Tdval2valwrt
Twrpulse
Valid address to valid chip select
1
1
4
4
Cycles
Cycles
Cycles
Cycles
ns
1, 2, 7
3, 7
Write data valid prior to EX_WR_N falling edge
Pulse width of the EX_WR_N
1
16
4
4, 7
Tdholdafterwr Valid data after the rising edge of EX_WR_N
1
5, 7
Trdsetup
Trdhold
Data valid required before the rising edge of EX_RD_N
Data hold required after the rising edge of EX_RD_N
15
0
ns
Time required between successive accesses on the
expansion interface.
Trecov
1
16
Cycles
6
Notes:
1.
2.
EX_ALE is not valid in simplex mode of operation.
Setting the address phase parameter (T1) will adjust the duration that the address appears to the
external device.
3.
4.
5.
6.
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a
data strobe (read or write) to an external device.
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears
(read or write) to an external device. Data will be available during this time as well.
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,
address, and data (during a write) will be held.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the expansion interface.
7.
8.
One cycle is the period of the Expansion Bus clock.
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
9.
Timing tests were performed with a 70-pF capacitor to ground.
March 2005
106
Datasheet
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
