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EPM3064ATC100-7N 参数 Datasheet PDF下载

EPM3064ATC100-7N图片预览
型号: EPM3064ATC100-7N
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 7.5ns, 64-Cell, CMOS, PQFP100, TQFP-100]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 46 页 / 711 K
品牌: INTEL [ INTEL ]
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MAX 3000A Programmable Logic Device Family Data Sheet  
MAX 3000A device timing can be analyzed with the Altera software, with  
Timing Model  
a variety of popular industry–standard EDA simulators and timing  
analyzers, or with the timing model shown in Figure 10. MAX 3000A  
devices have predictable internal delays that enable the designer to  
determine the worst–case timing of any design. The software provides  
timing simulation, point–to–point delay prediction, and detailed timing  
analysis for device–wide performance evaluation.  
Figure 10. MAX 3000A Timing Model  
Internal Output  
Enable Delay  
tIOE  
Global Control  
Delay  
Input  
Delay  
tIN  
Output  
Delay  
tGLOB  
Register  
Delay  
tSU  
Parallel  
Expander Delay  
tPEXP  
Logic Array  
Delay  
tLAD  
tOD1  
tOD2  
tOD3  
tXZ  
tZX1  
tZX2  
tZX3  
PIA  
Delay  
tPIA  
tH  
tPRE  
tCLR  
tRD  
Register  
Control Delay  
tCOMB  
tLAC  
tIC  
tEN  
I/O  
Delay  
tIO  
Shared  
Expander Delay  
tSEXP  
The timing characteristics of any signal path can be derived from the  
timing model and parameters of a particular device. External timing  
parameters, which represent pin–to–pin timing delays, can be calculated  
as the sum of internal parameters. Figure 11 shows the timing relationship  
between internal and external delay parameters.  
26  
Altera Corporation  
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