Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
5–11
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis independent of device
density.
through
describe the MAX II device internal timing
microparameters for logic elements (LEs), input/output elements (IOEs), UFM
blocks, and MultiTrack interconnects. The timing values for –3, –4, and –5 speed
grades shown in
through
are based on an EPM1270 device
target, while –6, –7, and –8 speed grade values are based on an EPM570Z device
target.
f
For more explanations and descriptions about each internal timing microparameters
symbol, refer to the
chapter in the
MAX II
Device Handbook.
Table 5–15.
LE Internal Timing Microparameters
MAX II / MAX IIG
–3 Speed
Grade
Symbol
t
LUT
t
COM B
t
CLR
t
PRE
t
SU
t
H
t
CO
t
CLK HL
t
C
Parameter
LE combinational
LUT delay
Combinational
path delay
LE register clear
delay
LE register preset
delay
LE register setup
time before clock
LE register hold
time after clock
LE register clock-
to-output delay
Minimum clock
high or low time
Register control
delay
Min
—
—
238
238
208
0
—
166
—
Max
571
147
—
—
—
—
235
—
857
–4 Speed
Grade
Min
—
—
309
309
271
0
—
216
—
Max
742
192
—
—
—
—
305
—
1,114
–5 Speed
Grade
Min
—
—
381
381
333
0
—
266
—
Max
914
236
—
—
—
—
376
—
1,372
–6 Speed
Grade
Min
—
—
401
401
260
0
—
253
—
Max
1,215
243
—
—
—
—
380
—
1,356
MAX IIZ
–7 Speed
Grade
Min
—
—
541
541
319
0
—
335
—
Max
2,247
305
—
—
—
—
489
—
1,722
–8 Speed
Grade
Min
—
—
545
545
321
0
—
339
—
Max
2,247
309
—
—
—
—
494
—
1,741
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
INTEL [ INTEL CORPORATION ]
