Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
5–9
Figure 5–2.
MAX II Device Timing Model
Output and Output Enable
Data Delay
t
R4
Data-In/LUT Chain
User
Flash
Memory
Logic Element
LUT Delay
t
IODR
t
IOE
t
C4
Output Routing
Delay
t
LOCAL
t
LUT
Register Control
Delay
t
COMB
t
CO
t
SU
t
H
t
PRE
t
CLR
t
FASTIO
I/O Input Delay
t
IN
Input Routing
Delay
t
DL
Output
Delay
t
OD
t
XZ
t
ZX
I/O Pin
t
C
I/O Pin
INPUT
t
GLOB
Global Input Delay
To Adjacent LE
Register Delays
From Adjacent LE
Combinational Path Delay
Data-Out
The timing characteristics of any signal path can be derived from the timing model
and parameters of a particular device. External timing parameters, which represent
pin-to-pin timing delays, can be calculated as the sum of internal parameters.
f
Refer to the
chapter in the
MAX II Device
Handbook
for more information.
This section describes and specifies the performance, internal, external, and UFM
timing specifications. All specifications are representative of the worst-case supply
voltage and junction temperature conditions.
Preliminary and Final Timing
Timing models can have either preliminary or final status. The Quartus II software
issues an informational message during the design compilation if the timing models
are preliminary.
shows the status of the MAX II device timing models.
Preliminary status means the timing model is subject to change. Initially, timing
numbers are created using simulation results, process data, and other known
parameters. These tests are used to make the preliminary numbers as close to the
actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing. These
numbers reflect the actual performance of the device under the worst-case voltage
and junction temperature conditions.
Table 5–13.
MAX II Device Timing Model Status
Device
EPM240
EPM240Z
EPM570
EPM570Z
Preliminary
—
—
—
—
(Part 1 of 2)
Final
v
v
v
v
INTEL [ INTEL CORPORATION ]
