5–10
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–13.
MAX II Device Timing Model Status
Device
EPM1270
EPM2210
Note to
(Part 2 of 2)
Final
v
v
Preliminary
—
—
(1) The MAX IIZ device timing models are only available in the Quartus II software
version 8.0 and later.
Performance
shows the MAX II device performance for some common designs. All
performance values were obtained with the Quartus II software compilation of
megafunctions. Performance values for –3, –4, and –5 speed grades are based on an
EPM1270 device target, while –6, –7, and –8 speed grades are based on an EPM570Z
device target.
Table 5–14.
MAX II Device Performance
Performance
Resources Used
Resource
Used
LE
Design Size and
Function
16-bit counter
64-bit counter
16-to-1 multiplexer
32-to-1 multiplexer
16-bit XOR function
16-bit decoder with
single address line
UFM
512 × 16
512 × 16
512 × 8
512 × 16
Notes to
(1) This design is a binary loadable up counter.
(2) This design is configured for read-only operation in Extended mode. Read and write ability increases the number of LEs used.
(3) This design is configured for read-only operation. Read and write ability increases the number of LEs used.
(4) This design is asynchronous.
(5) The I
2
C megafunction is verified in hardware up to 100-kHz serial clock line (SCL) rate.
MAX II / MAX IIG
–3
Speed
Grade
304.0
201.5
6.0
7.1
5.1
5.2
10.0
8.0
100
–4
Speed
Grade
247.5
154.8
8.0
9.0
6.6
6.6
10.0
8.0
100
–5
Speed
Grade
201.1
125.8
9.3
11.4
8.2
8.2
10.0
8.0
100
–6
Speed
Grade
184.1
83.2
17.4
12.5
9.0
9.2
10.0
9.7
100
MAX IIZ
–7
Speed
Grade
123.5
83.2
17.3
22.8
15.0
15.0
10.0
9.7
100
–8
Speed
Grade
118.3
80.5
20.4
25.3
16.1
16.1
10.0
9.7
100
Mode
—
—
—
—
—
—
None
SPI
Parallel
I
2
C
LEs
16
64
11
24
5
5
3
37
73
142
UFM
Blocks
0
0
0
0
0
0
1
1
1
1
Unit
MHz
MHz
ns
ns
ns
ns
MHz
MHz
MHz
kHz
INTEL [ INTEL CORPORATION ]
