欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM1270GT144C5N 参数 Datasheet PDF下载

EPM1270GT144C5N图片预览
型号: EPM1270GT144C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 10ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 88 页 / 982 K
品牌: INTEL [ INTEL ]
 浏览型号EPM1270GT144C5N的Datasheet PDF文件第40页浏览型号EPM1270GT144C5N的Datasheet PDF文件第41页浏览型号EPM1270GT144C5N的Datasheet PDF文件第42页浏览型号EPM1270GT144C5N的Datasheet PDF文件第43页浏览型号EPM1270GT144C5N的Datasheet PDF文件第45页浏览型号EPM1270GT144C5N的Datasheet PDF文件第46页浏览型号EPM1270GT144C5N的Datasheet PDF文件第47页浏览型号EPM1270GT144C5N的Datasheet PDF文件第48页  
3–2  
Chapter 3: JTAG and In-System Programmability  
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support  
Table 3–1. MAX II JTAG Instructions (Part 2 of 2)  
JTAG Instruction  
CLAMP(1)  
Instruction Code  
Description  
00 0000 1010  
Places the 1-bit bypass register between the TDIand TDOpins,  
which allows the boundary scan test data to pass synchronously  
through selected devices to adjacent devices during normal device  
operation, while holding I/O pins to a state defined by the data in the  
boundary-scan register.  
USER0  
USER1  
00 0000 1100  
00 0000 1110  
(2)  
This instruction allows you to define the scan chain between TDI  
and TDO in the MAX II logic array. This instruction is also used for  
custom logic and JTAG interfaces.  
This instruction allows you to define the scan chain between TDI  
and TDOin the MAX II logic array. This instruction is also used for  
custom logic and JTAG interfaces.  
IEEE 1532  
instructions  
IEEE 1532 ISC instructions used when programming a MAX II device  
via the JTAG port.  
Notes to Table 3–1:  
(1) HIGHZ, CLAMP, and EXTESTinstructions do not disable weak pull-up resistors or bus hold features.  
(2) These instructions are shown in the 1532 BSDL files, which will be posted on the Altera® website at www.altera.com when they are available.  
w
Unsupported JTAG instructions should not be issued to the MAX II device as this may  
put the device into an unknown state, requiring a power cycle to recover device  
operation.  
The MAX II device instruction register length is 10 bits and the USERCODEregister  
length is 32 bits. Table 3–2 and Table 3–3 show the boundary-scan register length and  
device IDCODEinformation for MAX II devices.  
Table 3–2. MAX II Boundary-Scan Register Length  
Device  
EPM240  
Boundary-Scan Register Length  
240  
480  
636  
816  
EPM570  
EPM1270  
EPM2210  
Table 3–3. 32-Bit MAX II Device IDCODE (Part 1 of 2)  
Binary IDCODE (32 Bits) (1)  
Version  
Manufacturer  
LSB  
Device  
EPM240  
(4 Bits)  
Part Number  
Identity (11 Bits)  
(1 Bit) (2)  
HEX IDCODE  
0000  
0010 0000 1010 0001  
000 0110 1110  
000 0110 1110  
000 0110 1110  
000 0110 1110  
1
1
1
1
0x020A10DD  
EPM240G  
EPM570  
0000  
0000  
0000  
0010 0000 1010 0010  
0010 0000 1010 0011  
0010 0000 1010 0100  
0x020A20DD  
0x020A30DD  
0x020A40DD  
EPM570G  
EPM1270  
EPM1270G  
EPM2210  
EPM2210G  
MAX II Device Handbook  
© October 2008 Altera Corporation  
 复制成功!