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EPM1270GT144C5N 参数 Datasheet PDF下载

EPM1270GT144C5N图片预览
型号: EPM1270GT144C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 10ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 88 页 / 982 K
品牌: INTEL [ INTEL ]
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Chapter 2: MAX II Architecture  
2–25  
I/O Structure  
Figure 2–20 shows how a row I/O block connects to the logic array.  
Figure 2–20. Row I/O Block Connection to the Interconnect (Note 1)  
R4 Interconnects  
C4 Interconnects  
I/O Block Local  
Interconnect  
data_out  
[6..0]  
7
OE  
[6..0]  
7
LAB  
Row  
I/O Block  
fast_out  
[6..0]  
7
7
data_in[6..0]  
Direct Link  
Interconnect  
from Adjacent LAB  
Direct Link  
Interconnect  
Row I/O Block  
Contains up to  
Seven IOEs  
to Adjacent LAB  
LAB Column  
clock [3..0]  
LAB Local  
Interconnect  
Note to Figure 2–20:  
(1) Each of the seven IOEs in the row I/O block can have one data_outor fast_outoutput, one OEoutput, and one data_ininput.  
© October 2008 Altera Corporation  
MAX II Device Handbook  
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