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EPM1270GT144C5N 参数 Datasheet PDF下载

EPM1270GT144C5N图片预览
型号: EPM1270GT144C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 10ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 88 页 / 982 K
品牌: INTEL [ INTEL ]
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Chapter 2: MAX II Architecture  
2–23  
I/O Structure  
I/O Structure  
IOEs support many features, including:  
LVTTL and LVCMOS I/O standards  
3.3-V, 32-bit, 66-MHz PCI compliance  
Joint Test Action Group (JTAG) boundary-scan test (BST) support  
Programmable drive strength control  
Weak pull-up resistors during power-up and in system programming  
Slew-rate control  
Tri-state buffers with individual output enable control  
Bus-hold circuitry  
Programmable pull-up resistors in user mode  
Unique output enable per pin  
Open-drain outputs  
Schmitt trigger inputs  
Fast I/O connection  
Programmable input delay  
MAX II device IOEs contain a bidirectional I/O buffer. Figure 2–19 shows the MAX II  
IOE structure. Registers from adjacent LABs can drive to or be driven from the IOE’s  
bidirectional I/O buffers. The Quartus II software automatically attempts to place  
registers in the adjacent LAB with fast I/O connection to achieve the fastest possible  
clock-to-output and registered output enable timing. For input registers, the  
Quartus II software automatically routes the register to guarantee zero hold time.  
You can set timing assignments in the Quartus II software to achieve desired I/O  
timing.  
Fast I/O Connection  
A dedicated fast I/O connection from the adjacent LAB to the IOEs within an I/O  
block provides faster output delays for clock-to-output and tPD propagation delays.  
This connection exists for data output signals, not output enable signals or input  
signals. Figure 2–20, Figure 2–21, and Figure 2–22 illustrate the fast I/O connection.  
© October 2008 Altera Corporation  
MAX II Device Handbook  
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