Chapter 2: MAX II Architecture
I/O Structure
2–27
describes the I/O standards supported by MAX II devices.
Table 2–4.
MAX II I/O Standards
I/O Standard
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
Note to
(1) The 3.3-V PCI compliant I/O is supported in Bank 3 of the EPM1270 and EPM2210
devices.
Type
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Output Supply Voltage
(VCCIO) (V)
3.3
2.5
1.8
1.5
3.3
The EPM240 and EPM570 devices support two I/O banks, as shown in
Each of these banks support all the LVTTL and LVCMOS standards shown in
PCI compliant I/O is not supported in these devices and banks.
Figure 2–22.
MAX II I/O Banks for EPM240 and EPM570
I/O Bank 1
I/O Bank 2
All I/O Banks Support
■
3.3-V LVTTL/LVCMOS
■
2.5-V LVTTL/LVCMOS
■
1.8-V LVTTL/LVCMOS
■
1.5-V LVCMOS
Notes to
(1)
is a top view of the silicon die.
(2)
is a graphical representation only. Refer to the pin list and the Quartus II software for exact pin locations.
The EPM1270 and EPM2210 devices support four I/O banks, as shown in
Each of these banks support all of the LVTTL and LVCMOS standards shown in
PCI compliant I/O is supported in Bank 3. Bank 3 supports the PCI
clamping diode on inputs and PCI drive compliance on outputs. You must use Bank 3
for designs requiring PCI compliant I/O pins. The Quartus II software automatically
places I/O pins in this bank if assigned with the PCI I/O standard.
INTEL [ INTEL CORPORATION ]
