Timing Model & Specifications
Table 5–28. External Timing Input Delay tGLOB Adders for GCLK Pins
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Standard
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
Min
Max
Min
Max
Min
Max
3.3-V LVTTL
Without Schmitt
Trigger
0
0
0
With Schmitt
Trigger
308
0
400
0
493
0
3.3-V LVCMOS Without Schmitt
Trigger
With Schmitt
Trigger
308
21
400
27
493
33
2.5-V LVTTL
Without Schmitt
Trigger
With Schmitt
Trigger
423
353
855
6
550
459
1,111
7
677
565
1,368
9
1.8-V LVTTL
1.5-V LVTTL
3.3-V PCI
Without Schmitt
Trigger
Without Schmitt
Trigger
Without Schmitt
Trigger
Table 5–29. External Timing Output Delay & tOD Adders for Fast Slew Rate
-3 Speed Grade -4 Speed Grade
-5 Speed Grade
Standard
Unit
Min
Max
Min
Max
Min
Max
3.3-V LVTTL
16 mA
8 mA
8 mA
4 mA
14 mA
7 mA
6 mA
3 mA
4 mA
2 mA
20 mA
0
65
0
84
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
104
0
3.3-V LVCMOS
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
3.3-V PCI
0
0
65
84
104
195
309
909
1,046
1,694
1,867
5
122
193
568
654
1,059
1,167
3
158
251
738
850
1,376
1,517
4
5–26
Core Version a.b.c variable
Altera Corporation
July 2006
MAX II Device Handbook, Volume 1
INTEL [ INTEL ]
