DC & Switching Characteristics
External Timing I/O Delay Adders
I/O delay timing parameters for I/O standard input and output adders
and input delays are specified by speed grade independent of device
density.
Tables 5–27 through 5–31 show the adder delays associated with I/O pins
for all packages. If an I/O standard other than 3.3-V LVTTL is selected,
add the input delay adder to the external tSU timing parameters shown in
Tables 5–23 through 5–26. If an I/O standard other than 3.3-V LVTTL
with 16 mA drive strength and fast slew rate is selected, add the output
delay adder to the external tCO and tPD shown in Tables 5–23 through
5–26.
Table 5–27. External Timing Input Delay Adders
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Standard
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
Min
Max
Min
Max
Min
Max
3.3-V LVTTL
Without Schmitt
0
0
0
Trigger
With Schmitt
Trigger
334
0
434
0
535
0
3.3-V LVCMOS Without Schmitt
Trigger
With Schmitt
Trigger
334
23
434
30
535
37
2.5-V LVTTL
Without Schmitt
Trigger
With Schmitt
Trigger
339
291
681
0
441
378
885
0
543
466
1,090
0
1.8-V LVTTL
1.5-V LVTTL
3.3-V PCI
Without Schmitt
Trigger
Without Schmitt
Trigger
Without Schmitt
Trigger
Altera Corporation
July 2006
Core Version a.b.c variable
5–25
MAX II Device Handbook, Volume 1
INTEL [ INTEL ]
