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EPM1270GF100I4N 参数 Datasheet PDF下载

EPM1270GF100I4N图片预览
型号: EPM1270GF100I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-100]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 98 页 / 1060 K
品牌: INTEL [ INTEL ]
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Introduction  
1
For more information on equivalent macrocells, refer to the  
MAX II Logic Element to Macrocell Conversion Methodology white  
paper.  
MAX II devices are available in three speed grades: -3, -4, -5 with -3 being  
the fastest. These speed grades represent overall relative performance,  
not any specific timing parameter. For propagation delay timing  
numbers within each speed grade and density, see the chapter on DC &  
Switching Characteristics. Table 1–2 shows MAX II device speed-grade  
offerings.  
Table 1–2. MAX II Speed Grades  
Speed Grade  
Device  
-3  
-4  
-5  
EPM240  
EPM570  
EPM1270  
EPM2210  
v
v
v
v
v
v
v
v
v
v
v
v
®
MAX II devices are available in space-saving FineLine BGA , Micro  
FineLine BGA, and thin quad flat pack (TQFP) packages (see Tables 1–3  
and 1–4). MAX II devices support vertical migration within the same  
package (e.g., you can migrate between the EPM570, EPM1270, and  
EPM2210 devices in the  
256-pin FineLine BGA package). Vertical migration means that you can  
migrate to devices whose dedicated pins and JTAG pins are the same and  
power pins are subsets or supersets for a given package across device  
densities. The largest density in any package has the highest number of  
power pins; you must layout for the largest planned density in a package  
to provide the necessary power pins for migration. For I/O pin migration  
across densities, cross reference the available I/O pins using the device  
pin-outs for all planned densities of a given package type to identify  
which I/O pins can be migrated. The Quartus® II software can  
automatically cross reference and place all pins for you when given a  
device migration list.  
Altera Corporation  
August 2006  
Core Version a.b.c variable  
1–3  
MAX II Device Handbook, Volume 1  
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