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EP3C16M164C8N 参数 Datasheet PDF下载

EP3C16M164C8N图片预览
型号: EP3C16M164C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 15408-Cell, CMOS, PBGA164, LEAD FREE, MBGA-164]
分类和应用: 可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL CORPORATION ]
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1–8
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
shows you the example to calculate the change of 50
I/O
impedance
from 25°C at 3.0 V to 85°C at 3.15 V:
Example 1–1.
R
V
= (3.15 – 3) × 1000 × –0.026 = –3.83
R
T
= (85 – 25) × 0.262 = 15.72
Because
R
V
is negative,
MF
V
= 1 / (3.83/100 + 1) = 0.963
Because
R
T
is positive,
MF
T
= 15.72/100 + 1 = 1.157
MF = 0.963 × 1.157 = 1.114
R
final
= 50 × 1.114 = 55.71
Pin Capacitance
lists the pin capacitance for Cyclone III devices.
Table 1–9. Cyclone III Devices Pin Capacitance
Symbol
C
IOTB
C
IOLR
C
LVDSLR
C
VREFLR
Parameter
Input capacitance on top/bottom I/O pins
Input capacitance on left/right I/O pins
Input capacitance on left/right I/O pins with dedicated
LVDS output
Input capacitance on left/right dual-purpose
VREF
pin
when used as V
REF
or user I/O pin
Input capacitance on top/bottom dual-purpose
VREF
pin
when used as V
REF
or user I/O pin
Input capacitance on top/bottom dedicated clock input
pins
Input capacitance on left/right dedicated clock input pins
Typical –
QFP
7
7
8
21
23
7
6
Typical –
FBGA
6
5
7
21
23
6
5
Unit
pF
pF
pF
pF
pF
pF
pF
C
VREFTB
C
CLKTB
C
CLKLR
Notes to
(1) When
VREF
pin is used as regular input or output, a reduced performance of toggle rate and t
CO
is expected due to
higher pin capacitance.
(2) C
VREFTB
for EP3C25 is 30 pF.
July 2012 Altera Corporation