欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP2S130F1020I4N 参数 Datasheet PDF下载

EP2S130F1020I4N图片预览
型号: EP2S130F1020I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 6627 CLBs, 717MHz, 132540-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020]
分类和应用: 时钟可编程逻辑
文件页数/大小: 248 页 / 2983 K
品牌: INTEL [ INTEL ]
 浏览型号EP2S130F1020I4N的Datasheet PDF文件第80页浏览型号EP2S130F1020I4N的Datasheet PDF文件第81页浏览型号EP2S130F1020I4N的Datasheet PDF文件第82页浏览型号EP2S130F1020I4N的Datasheet PDF文件第83页浏览型号EP2S130F1020I4N的Datasheet PDF文件第85页浏览型号EP2S130F1020I4N的Datasheet PDF文件第86页浏览型号EP2S130F1020I4N的Datasheet PDF文件第87页浏览型号EP2S130F1020I4N的Datasheet PDF文件第88页  
PLLs & Clock Networks  
Table 2–11. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs (Part 2  
of 2)  
Top Side Global & Regional  
Clock Network Connectivity  
c4  
v
v
v
v
v
v
v
v
c5  
v
v
v
v
v
v
Enhanced PLL 11 outputs  
c0  
v
v
v
v
c1  
c2  
c3  
c4  
c5  
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Table 2–12. Global & Regional Clock Connections from Bottom Clock Pins & Enhanced PLL  
Outputs (Part 1 of 2)  
Bottom Side Global &  
Regional Clock Network  
Connectivity  
Clock pins  
CLK4p  
v
v
v
v
v
v
v
v
v
v
v
v
CLK5p  
CLK6p  
CLK7p  
CLK4n  
CLK5n  
CLK6n  
CLK7n  
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Drivers from internal logic  
GCLKDRV0  
GCLKDRV1  
GCLKDRV2  
2–66  
Altera Corporation  
May 2007  
Stratix II Device Handbook, Volume 1  
 复制成功!