Stratix II Architecture
Figure 2–41. Global & Regional Clock Connections from Center Clock Pins &
Fast PLL Outputs
Note (1)
Notes to Figure 2–41:
(1) EP2S15 and EP2S30 devices only have four fast PLLs (1, 2, 3, and 4), but the
connectivity from these four PLLs to the global and regional clock networks
remains the same as shown.
(2) The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input.
The global or regional clock input can be driven by an output from another PLL, a
pin-driven dedicated global or regional clock, or through a clock control block,
provided the clock control block is fed by an output from another PLL or a
pin-driven dedicated global or regional clock. An internally generated global
signal cannot drive the PLL.
Altera Corporation
May 2007
2–61
Stratix II Device Handbook, Volume 1
INTEL [ INTEL ]
