2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
Table 2. 28F200/002 Pin Descriptions
Name and Function
Symbol
WP#
Type
INPUT
WRITE PROTECT: Provides a method for unlocking the boot block in a system
without a 12 V supply.
When WP# is at logic low, the boot block is locked, preventing program and
erase operations to the boot block. If a program or erase operation is attempted
on the boot block when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the status register to indicate the operation
failed.
When WP# is at logic high, the boot block is unlocked and can be
programmed or erased.
NOTE: This feature is overridden and the boot block unlocked when RP# is at
V
HH. See Section 3.4 for details on write protection.
BYTE#
INPUT
BYTE# ENABLE: Not available on 28F002B. Controls whether the device
operates in the byte-wide mode (x8) or the word-wide mode (x16). BYTE# pin
must be controlled at CMOS levels to meet the CMOS current specification in the
standby mode.
When BYTE# is at logic low, the byte-wide mode is enabled, where data is
read and programmed on DQ0–DQ7 and DQ15/A–1 becomes the lowest order
address that decodes between the upper and lower byte. DQ8–DQ14 are tri-stated
during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is enabled, where data is
read and programmed on DQ0–DQ15
.
VCC
VPP
DEVICE POWER SUPPLY: 5.0 V ± 10%, 3.3 V ± 0.3 V, 2.7 V–3.6 V (BE/CE
only)
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block, a voltage either of 5 V ± 10% or 12 V ± 5% must
be applied to this pin. When VPP < VPPLK all blocks are locked and protected
against Program and Erase commands.
GND
NC
GROUND: For all internal circuitry.
NO CONNECT: Pin may be driven or left floating.
12
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INTEL [ INTEL ]
