28F320J5 and 28F640J5
3.7
Write
Writing commands to the CUI enables reading of device data, query, identifier codes, inspection
and clearing of the status register, and, when VPEN = VPENH, block erasure, program, and lock-bit
configuration.
The Block Erase command requires appropriate command data and an address within the block to
be erased. The Byte/Word Program command requires the command and address of the location to
be written. Set Master and Block Lock-Bit commands require the command and address within the
device (Master Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-
Bits command requires the command and address within the device.
The CUI does not occupy an addressable memory location. It is written when the device is enabled
and WE# is active. The address and data needed to execute a command are latched on the rising
edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 2 on
page 12). Standard microprocessor write timings are used.
Table 3. Bus Operations
STS
(default
mode)
(1)
Mode
Notes
RP#
CE
OE#(2) WE#(2) Address
V
DQ(3)
0,1,2
PEN
Read Array
Output Disable
Standby
4,5,6
V
V
V
or V
or V
or V
Enabled
Enabled
Disabled
V
V
V
X
X
X
X
X
X
D
High Z(7)
IH
IH
IH
HH
HH
HH
IL
IH
OUT
V
Hig
h Z
X
IH
IH
X
X
High Z
X
Reset/Power-
Down Mode
(7)
V
X
X
X
X
X
X
X
X
Hig h Z
Note 8
Note 9
Hig h Z
IL
Read Identifier
Codes
See
Figure 5
(7)
V
V
V
or V
or V
or V
Enabled
Enabled
Enabled
V
V
Hig h Z
IH
IH
IH
HH
HH
HH
IL
IL
IL
IH
IH
IH
See
Table 7
(7)
Read Query
V
V
V
V
Hig h Z
Read Status
(WSM off)
X
D
OUT
DQ = D
7
OUT
Read Status
(WSM on)
V
V
or V
or V
Enabled
Enabled
V
V
X
X
V
DQ
DQ
= Hig h Z
= Hig h Z
IH
IH
HH
HH
IL
IH
PENH
15–8
6–0
Write
6,10,11
V
V
X
D
IN
X
IH
IL
NOTES:
1. See Table 2 for valid CE configurations.
2. OE# and WE# should never be enabled simultaneously.
3. DQ refers to DQ –DQ if BYTE# is low and DQ –DQ if BYTE# is high.
0
7
0
15
4. Refer to DC Characteristics. When V
≤ V
, memory contents can be read, but not altered.
PEN
PENLK
5. X can be V or V for control and address pins, and V
or V
for V
. See DC Characteristics for
IL
and V
IH
PENLK
PENH
PEN
V
voltages.
PENLK
PENH
6. In default mode, STS is V when the WSM is executinginternal block erase, program, or lock-bit
OL
configuration algorithms. It is V when the WSM is not busy, in block erase suspend mode (with
programming inactive), or reset/power-down mode.
OH
7. High Z will be V with an external pull-up resistor.
OH
8. See Read Identifier Codes Command section for read identifier code data.
9. See Read Query Mode Command section for read query data.
10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when V
=
PEN
V
and V is within specification. Block erase, program, or lock-bit configuration with V < RP# < V
PENH
CC IH HH
produce spurious results and should not be attempted.
11.Refer to Table 4 for valid D duringa write operation.
IN
16
Datasheet
INTEL [ INTEL ]
