28F320J5 and 28F640J5
4.0
Command Definitions
When the VPEN voltage ≤ VPENLK, only read operations from the status register, query, identifier
codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase, program,
and lock-bit configuration operations.
Device operations are selected by writing specific commands into the CUI. Table 4 defines these
commands.
Table 4. Intel StrataFlash® Memory Command Set Definitions(1,2)
Scaleable
Bus
or Basic
Command
Cycles
Req’d.
Notes
First Bus Cycle
Second Bus Cycle
Command
Set(2)
Oper(3)
Addr(4)
Data(5,6)
Oper(3)
Addr(4)
Data(5,6)
Read Array
SCS/BCS
SCS/BCS
SCS
1
Write
X
FFH
Read Identifier
Codes
≥ 2
≥ 2
2
7
8
Write
Write
Write
X
X
X
90H
98H
70H
Read
Read
Read
IA
QA
X
ID
Read Query
QD
Read Status
Register
SCS/BCS
SRD
Clear Status
Register
SCS/BCS
SCS/BCS
1
Write
Write
X
50H
E8H
9, 10,
11
Write to Buffer
> 2
BA
Write
BA
N
40H
or
10H
Word/Byte
Program
SCS/BCS
SCS/BCS
SCS/BCS
2
2
1
12,13
11,12
12,14
Write
Write
Write
X
X
X
Write
Write
PA
BA
PD
Block Erase
20H
D0H
Block Erase,
Program
B0H
Suspend
Block Erase,
Program
Resume
SCS/BCS
SCS
1
12
Write
X
D0H
Configuration
2
2
Write
Write
X
X
B8H
60H
Write
Write
X
CC
Set Read
Configuration
RCD
03H
Set Block Lock-
Bit
SCS
SCS
2
2
2
Write
Write
Write
X
X
X
60H
60H
C0H
Write
Write
Write
BA
X
01H
D0H
PD
Clear Block
Lock-Bits
15
Protection
Program
PA
NOTES:
1. Commands other than those shown above are reserved by Intel for future device implementations and
should not be used.
2. If the WSM is running, only DQ is valid; DQ –DQ and DQ –DQ float, which places them in a hig h-
7
15
8
6
0
impedance state.
Datasheet
17
INTEL [ INTEL ]
