28F320J5 and 28F640J5
3.0
Bus Operation
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus cycles.
Figure 4. Memory Map
A [22-0]: 64-Mbit
A [21-0]: 32-Mbit
A [22-1]: 64-Mbit
A [21-1]: 32-Mbit
3FFFFF
7FFFFF
128-Kbyte Block
128-Kbyte Block
64-Kword Block
64-Kword Block
63
31
63
31
7E0000
3F0000
3FFFFF
3E0000
1FFFFF
1F0000
03FFFF
01FFFF
128-Kbyte Block
128-Kbyte Block
64-Kword Block
64-Kword Block
1
0
1
0
020000
01FFFF
010000
00FFFF
000000
000000
Byte-Wide (x8) Mode
Word Wide (x16) Mode
Table 2. Chip Enable Truth Table
CE
CE
CE
0
DEVICE
2
1
V
V
V
V
V
V
V
IL
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
IL
IL
V
IH
IL
IL
IL
IH
IH
V
V
V
IL
V
IL
IH
V
V
V
V
V
V
V
IH
IH
IH
IH
IL
IL
IL
V
IH
V
V
IH
IH
IL
V
V
IH
NOTES:
1. See Application Note, AP-647 5 Volt Intel StrataFlash® Memory Design Guide for typical CE configurations.
2. For single-chip applications CE and CE can be strapped to GND.
2
1
12
Datasheet
INTEL [ INTEL ]
