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DT28F320J5-120 参数 Datasheet PDF下载

DT28F320J5-120图片预览
型号: DT28F320J5-120
PDF下载: 下载PDF文件 查看货源
内容描述: 5伏英特尔的StrataFlash ?内存 [5 Volt Intel StrataFlash® Memory]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 51 页 / 620 K
品牌: INTEL [ INTEL ]
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28F320J5 and 28F640J5  
Table 1. Lead Descriptions  
Symbol  
Type  
Name and Function  
BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode.  
A
INPUT  
This address is latched duringa x8 program cycle. Not used in x16 mode (i.e., the A input buffer  
0
0
is turned off when BYTE# is high).  
ADDRESS INPUTS: Inputs for addresses duringread and program operations. Addresses are  
internally latched duringa program cycle.  
A –A  
INPUT  
1
22  
32-Mbit: A –A  
0
21  
22  
64-Mbit: A –A  
0
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs  
commands duringCommand User Interface (CUI) writes. Outputs array, query, identifier, or status  
data in the appropriate read mode. Floated when the chip is de-selected or the outputs are  
INPUT/  
OUTPUT  
DQ –DQ  
0
7
disabled. Outputs DQ –DQ are also floated when the Write State Machine (WSM) is busy. Check  
6
0
SR.7 (status register bit 7) to determine WSM status.  
HIGH-BYTE DATA BUS: Inputs data duringx16 buffer writes and programmingoperations.  
Outputs array, query, or identifier data in the appropriate read mode; not used for status register  
reads. Floated when the chip is de-selected, the outputs are disabled, or the WSM is busy.  
INPUT/  
OUTPUT  
DQ –DQ  
8
15  
CHIP ENABLES: Activates the device’s control logic, input buffers, decoders, and sense  
amplifiers. When the device is de-selected (see Table 2 on pag e 12, power reduces to standby  
levels.  
CE ,  
0
CE ,  
INPUT  
INPUT  
1
2
All timingspecifications are the same for these three signals. Device selection occurs with the first  
CE  
edge of CE , CE , or CE that enables the device. Device deselection occurs with the first edge of  
0
1
2
CE , CE , or CE that disables the device (see Table 2).  
0
1
2
RESET/ POWER-DOWN: Resets internal automation and puts the device in power-down mode.  
RP#-high enables normal operation. Exit from reset sets the device to read array mode. When  
driven low, RP# inhibits write operations which provides data protection duringpower transitions.  
RP#  
RP# at V enables master lock-bit settingand block lock-bits configuration when the master  
HH  
lock-bit is set. RP# = V overrides block lock-bits thereby enablingblock erase and  
programming operations to locked memory blocks. Do not permanently connect RP# to V  
HH  
.
HH  
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.  
OE# is active low.  
OE#  
WE#  
INPUT  
INPUT  
WRITE ENABLE: Controls writes to the Command User Interface, the Write Buffer, and array  
blocks. WE# is active low. Addresses and data are latched on the risingedge of the WE# pulse.  
STATUS: Indicates the status of the internal state machine. When configured in level mode  
(default mode), it acts as a RY/BY# pin. When configured in one of its pulse modes, it can pulse to  
indicate program and/or erase completion. For alternate configurations of the STATUS pin, see  
OPEN  
DRAIN  
OUTPUT  
STS  
the Configurations command. Tie STS to V  
with a pull-up resistor.  
CCQ  
BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or output on  
DQ –DQ , while DQ –DQ float. Address A selects between the high and low byte. BYTE# high  
0
7
8
15  
0
BYTE#  
INPUT  
places the device in x16 mode, and turns off the A input buffer. Address A then becomes the  
0
1
lowest order address.  
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasingarray blocks, programmingdata, or  
configuring lock-bits.  
V
INPUT  
PEN  
With V  
V  
, memory contents cannot be altered.  
PENLK  
PEN  
V
V
SUPPLY  
DEVICE POWER SUPPLY: With V V  
, all write attempts to the flash memory are inhibited.  
LKO  
CC  
CC  
OUTPUT  
BUFFER  
SUPPLY  
OUTPUT BUFFER POWER SUPPLY: This voltage controls the device’s output voltages. To  
obtain output voltages compatible with system data bus voltages, connect V  
supply voltage.  
to the system  
CCQ  
CCQ  
GND  
NC  
SUPPLY  
GROUND: Do not float any ground pins.  
NO CONNECT: Lead is not internally connected; it may be driven or floated.  
Datasheet  
9