Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.31
SKPD—Scratchpad Data (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
DCh
00000000h
R/W
Size:
32 bits
This register holds 32 writable bits with no functionality behind them. It is for the convenience of
BIOS and graphics drivers.
Bit
Access &
Default
Description
31:0
R/W
Scratchpad Data: 1 DWord of data storage.
00000000 h
4.1.32
CAPID0—Capability Identifier (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
E0h
000000000001090009h
RO
Size:
72 bits
Bit
Access &
Default
Description
71:28
27:24
Reserved
RO
1h
CAPID Version: This field has the value 0001b to identify the first revision of the
CAPID register definition.
23:16
15:8
7:0
RO
09h
CAPID Length: This field has the value 09h to indicate the structure length
(9 bytes).
RO
00h
Next Capability Pointer: This field is hardwired to 00h indicating the end of the
capabilities linked list.
RO
CAP_ID: This field has the value 1001b to identify the CAP_ID assigned by the
09h
PCI SIG for vendor dependent capability pointers.
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Datasheet
INTEL [ INTEL ]
