MCHBAR Registers
R
5 MCHBAR Registers
These registers are offset from the MCHBAR base address.
Address
Offset
Register
Symbol
Default
Access
Value
Register Name
100h
101h
C0DRB0
C0DRB1
C0DRB2
C0DRB3
—
Channel A DRAM Rank Boundary Address 0
Channel A DRAM Rank Boundary Address 1
Channel A DRAM Rank Boundary Address 2
Channel A DRAM Rank Boundary Address 3
Reserved
00h
00h
R/W
R/W
R/W
R/W
—
102h
00h
103h
00h
104–107h
108h
—
C0DRA0
C0DRA2
—
Channel A DRAM Rank 0,1 Attribute
Channel A DRAM Rank 2,3 Attribute
Reserved
00h
R/W
R/W
—
109h
00h
10A–10Bh
10Ch
—
C0DCLKDIS
—
Channel A DRAM Clock Disable
Reserved
00h
R/W
—
10Dh
—
10E–10F
110–113h
114–117h
118–11Fh
120–123h
124–17Fh
180h
C0BNKARC
—
Channel A DRAM Bank Architecture
Reserved
0000h
—
R/W
—
C0DRT1
—
Channel A DRAM Timing Register
Reserved
900122h
—
R/W
—
C0DRC0
—
Channel A DRAM Controller Mode 0
Reserved
00000000h
—
R/W, RO
—
C1DRB0
C1DRB1
C1DRB2
C1DRB3
—
Channel B DRAM Rank Boundary Address 0
Channel B DRAM Rank Boundary Address 1
Channel B DRAM Rank Boundary Address 2
Channel B DRAM Rank Boundary Address 3
Reserved
00h
R/W
R/W
R/W
R/W
—
181h
00h
182h
00h
183h
00h
184–187h
188h
—
C1DRA0
C1DRA2
—
Channel B DRAM Rank 0,1 Attribute
Channel B DRAM Rank 2,3 Attribute
Reserved
00h
R/W
R/W
—
189h
00h
18A–18Bh
18Ch
—
C1DCLKDIS
—
Channel B DRAM Clock Disable
Reserved
00h
R/W
—
18Dh
—
18E–18Fh
190–193h
194h
C1BNKARC
—
Channel B Bank Architecture
Reserved
0000h
—
R/W
—
C1DRT1
Channel B DRAM Timing Register 1
900122h
R/W, RO
Datasheet
95
INTEL [ INTEL ]
