Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.30
ERRCMD—Error Command (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
CAh
0000h
R/W
Size:
16 bits
This register controls the (G)MCH responses to various system errors. Since the (G)MCH does
not have an SERR# signal, SERR messages are passed from the (G)MCH to the Intel ICH6 over
DMI. When a bit in this register is set, a SERR message will be generated on DMI when the
corresponding flag is set in the ERRSTS register. The actual generation of the SERR message is
globally enabled for Device 0 via the PCI Command register.
Bit
Access &
Default
Description
15:12
11
Reserved
R/W
0b
SERR on (G)MCH Thermal Sensor Event (TSESERR)
1 = The (G)MCH generates a DMI SERR special cycle when bit 11 of the
ERRSTS is set. The SERR must not be enabled at the same time as the SMI
for the same thermal sensor event.
0 = Reporting of this condition via SERR messaging is disabled.
Reserved
10
9
R/W
0b
SERR on LOCK to non-DRAM Memory (LCKERR)
1 = The (G)MCH will generate a DMI SERR special cycle whenever a processor
lock cycle is detected that does not hit DRAM.
0 = Reporting of this condition via SERR messaging is disabled.
8
R/W
0b
SERR on DRAM Refresh Timeout (DRTOERR)
1 = The (G)MCH generates a DMI SERR special cycle when a DRAM Refresh
timeout occurs.
0 = Reporting of this condition via SERR messaging is disabled.
Reserved
7:0
Datasheet
93
INTEL [ INTEL ]
