Signal Description
R
2.11
Reset States and Pull-up/Pull-downs
This section describes the expected states of the (G)MCH I/O buffers during and immediately
after the assertion of RSTIN#. This table only refers to the contributions on the interface from the
(G)MCH and does not reflect any external influence (such as external pull-up/pull-down resistors
or external drivers).
Legend:
CMCT:
Common Mode Center Tapped. Differential signals are weakly driven to the common
mode central voltage.
DRIVE: Strong drive (to normal value supplied by core logic if not otherwise stated)
TERM:
LV:
Normal termination devices are turned on
Low voltage
HV:
IN:
High voltage
Input buffer enabled
ISO:
TRI:
PU:
Isolate input buffer so that it doesn’t oscillate if input left floating
Tri-state
Weak internal pull-up
Weak internal pull-down
PD:
STRAP: Strap input sampled during assertion or on the de-asserting edge of RSTIN#
Table 2-1. Host Interface Reset and S3 States
State During
State After
RSTIN# De-
assertion
S3
Pull-up/
Pull-down
Interface
Signal Name
I/O
RSTIN#
Assertion
Host I/F
HCPURST#
O
DRIVE LV
TERM HV after
TRI (No VTT)
approximately 1ms
HADSTB[1:0]#
HA[31:3]#
HD[63:0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
HDSTBP[3:0]#
HDSTBN[3:0]#
HDINV[3:0]#
HADS#
HBNR#
HBPRI#
HDBSY#
I/O
O
HDEFER#
HDRDY#
I/O
O
HEDRDY#
46
Datasheet
INTEL [ INTEL ]
