R
5.1.12 C1DRB1—Channel B DRAM Rank Boundary Address 1 ..................106
5.1.13 C1DRB2—Channel B DRAM Rank Boundary Address 2 ..................106
5.1.14 C1DRB3—Channel B DRAM Rank Boundary Address 3 ..................106
5.1.15 C1DRA0—Channel B DRAM Rank 0,1 Attribute ...............................106
5.1.16 C1DRA2—Channel B DRAM Rank 2,3 Attribute ...............................107
5.1.17 C1DCLKDIS—Channel B DRAM Clock Disable ................................107
5.1.18 C1BNKARC—Channel B Bank Architecture ......................................107
5.1.19 C1DRT1—Channel B DRAM Timing Register 1 ................................107
5.1.20 C1DRC0—Channel B DRAM Controller Mode 0 ...............................107
5.1.21 PMCFG—Power Management Configuration ....................................108
5.1.22 PMSTS—Power Management Status ................................................108
6
7
EPBAR Registers—Egress Port Register Summary......................................................109
6.1
EP RCRB Configuration Register Details ..........................................................109
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
EPESD—EP Element Self Description...............................................110
EPLE1D—EP Link Entry 1 Description ..............................................111
EPLE1A—EP Link Entry 1 Address....................................................111
EPLE2D—EP Link Entry 2 Description ..............................................112
EPLE2A—EP Link Entry 2 Address....................................................113
DMIBAR Registers—Direct Media Interface (DMI) RCRB .............................................115
7.1 Direct Media Interface (DMI) RCRB Register Details ........................................116
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
DMIVCECH—DMI Virtual Channel Enhanced Capability Header .....116
DMIPVCCAP1—DMI Port VC Capability Register 1..........................116
DMIPVCCAP2—DMI Port VC Capability Register 2..........................117
DMIPVCCTL—DMI Port VC Control ..................................................117
DMIVC0RCAP—DMI VC0 Resource Capability ................................118
DMIVC0RCTL0—DMI VC0 Resource Control ...................................119
DMIVC0RSTS—DMI VC0 Resource Status.......................................120
DMIVC1RCAP—DMI VC1 Resource Capability ................................120
DMIVC1RCTL1—DMI VC1 Resource Control ...................................121
7.1.10 DMIVC1RSTS—DMI VC1 Resource Status.......................................121
7.1.11 DMILCAP—DMI Link Capabilities ......................................................122
7.1.12 DMILCTL—DMI Link Control..............................................................122
7.1.13 DMILSTS—DMI Link Status ...............................................................123
8
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 125
8.1 Host-PCI Express* Bridge PCI Register Details (D1:F0)...................................128
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
VID1—Vendor Identification (D1:F0)..................................................128
DID1—Device Identification (D1:F0) ..................................................128
PCICMD1—PCI Command (D1:F0)...................................................129
PCISTS1—PCI Status (D1:F0)...........................................................130
RID1—Revision Identification (D1:F0)................................................132
CC1—Class Code (D1:F0) .................................................................132
CL1—Cache Line Size (D1:F0)..........................................................133
HDR1—Header Type (D1:F0) ............................................................133
PBUSN1—Primary Bus Number (D1:F0)...........................................133
8.1.10 SBUSN1—Secondary Bus Number (D1:F0) ......................................134
8.1.11 SUBUSN1—Subordinate Bus Number (D1:F0) .................................134
8.1.12 IOBASE1—I/O Base Address (D1:F0) ...............................................135
8.1.13 IOLIMIT1—I/O Limit Address (D1:F0) ................................................135
8.1.14 SSTS1—Secondary Status (D1:F0)...................................................136
8.1.15 MBASE1—Memory Base Address (D1:F0)........................................137
Datasheet
5
INTEL [ INTEL ]
