R
Contents
1
Introduction .......................................................................................................................17
1.1
1.2
1.3
Terminology..........................................................................................................24
Reference Documents..........................................................................................26
GMCH (MCH) Overview.......................................................................................26
1.3.1
1.3.2
1.3.3
1.3.4
Host Interface........................................................................................26
System Memory Interface.....................................................................27
Direct Media Interface (DMI).................................................................28
PCI Express* Graphics Interface (Intel® 82915G/82915P/
and 82915PL Only)...............................................................................28
Integrated Graphics (Intel® 82915G/82915GV/82910GL/82915GL
GMCH Only) .........................................................................................29
Analog and Intel® SDVO Displays (Intel®
1.3.5
1.3.6
82915G/82915GV/82910GL/82915GL GMCH Only) ...........................31
System Interrupts..................................................................................31
(G)MCH Clocking..................................................................................31
Power Management..............................................................................32
1.3.7
1.3.8
1.3.9
2
Signal Description .............................................................................................................33
2.1
2.2
2.3
2.4
2.5
Host Interface Signals ..........................................................................................35
DDR/DDR2 DRAM Channel A Interface ..............................................................38
DDR/DDR2 DRAM Channel B Interface ..............................................................39
DDR/DDR2 DRAM Reference and Compensation..............................................40
PCI Express* x16 Graphics Port Signals (Intel® 82915G, 82915P,
82915PL Only)......................................................................................................41
2.6
Analog Display Signals (Intel® 82915G/82915GV/82915GL/82910GL
GMCH Only).........................................................................................................42
2.7
2.8
2.9
Clocks, Reset, and Miscellaneous .......................................................................43
Direct Media Interface (DMI) ................................................................................43
Intel® Serial DVO (SDVO) Interface (82915G/82915GV/82915GL/82910GL
GMCH Only).........................................................................................................44
2.10
2.11
Power and Ground ...............................................................................................45
Reset States and Pull-up/Pull-downs...................................................................46
3
Register Description..........................................................................................................53
3.1
3.2
3.3
Register Terminology ...........................................................................................53
Platform Configuration..........................................................................................55
General Routing Configuration Accesses............................................................58
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
Standard PCI Bus Configuration Mechanism.......................................58
Logical PCI Bus 0 Configuration Mechanism.......................................58
Primary PCI and Downstream Configuration Mechanism....................59
PCI Express* Enhanced Configuration Mechanism.............................60
Intel® 915x GMCH Configuration Cycle Flowchart ...............................62
3.4
I/O Mapped Registers ..........................................................................................63
3.4.1
CONFIG_ADDRESS—Configuration Address Register ......................63
Datasheet
3
INTEL [ INTEL ]
