R
3.4.2
CONFIG_DATA—Configuration Data Register....................................64
4
Host Bridge/DRAM Controller Registers (D0:F0) .............................................................65
4.1 Host Bridge/DRAM Controller PCI Register Details (D0:F0) ...............................68
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
VID—Vendor Identification (D0:F0)......................................................68
DID—Device Identification (D0:F0) ......................................................68
PCICMD—PCI Command (D0:F0).......................................................69
PCISTS—PCI Status (D0:F0)...............................................................70
RID—Revision Identification (D0:F0)....................................................71
CC—Class Code (D0:F0) .....................................................................71
MLT—Master Latency Timer (D0:F0)...................................................72
HDR—Header Type (D0:F0) ................................................................72
SVID—Subsystem Vendor Identification (D0:F0).................................72
4.1.10 SID—Subsystem Identification (D0:F0)................................................73
4.1.11 CAPPTR—Capabilities Pointer (D0:F0) ...............................................73
4.1.12 EPBAR—Egress Port Base Address (D0:F0) ......................................74
4.1.13 MCHBAR—(G)MCH Memory Mapped Register Range Base Address
(D0:F0)..................................................................................................75
4.1.14 PCIEXBAR—PCI Express* Register Range Base Address (D0:F0)
(Intel® 82915G/82915P/82915PL Only)................................................76
4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) ......77
4.1.16 GGC—GMCH Graphics Control Register (D0:F0)
(82915G/82915GV/82915GL/82910GL GMCH only)...........................78
4.1.17 DEVEN—Device Enable (D0:F0) .........................................................79
4.1.18 PAM0—Programmable Attribute Map 0 (D0:F0)..................................81
4.1.19 PAM1—Programmable Attribute Map 1 (D0:F0)..................................82
4.1.20 PAM2—Programmable Attribute Map 2 (D0:F0)..................................83
4.1.21 PAM3—Programmable Attribute Map 3 (D0:F0)..................................84
4.1.22 PAM4—Programmable Attribute Map 4 (D0:F0)..................................85
4.1.23 PAM5—Programmable Attribute Map 5 (D0:F0)..................................86
4.1.24 PAM6—Programmable Attribute Map 6 (D0:F0)..................................87
4.1.25 LAC—Legacy Access Control (D0:F0).................................................88
4.1.26 TOLUD—Top of Low Usable DRAM (D0:F0).......................................89
4.1.27 SMRAM—System Management RAM Control (D0:F0)........................90
4.1.28 ESMRAMC—Extended System Management RAM Control (D0:F0) ..91
4.1.29 ERRSTS—Error Status (D0:F0) ...........................................................92
4.1.30 ERRCMD—Error Command (D0:F0) ...................................................93
4.1.31 SKPD—Scratchpad Data (D0:F0) ........................................................94
4.1.32 CAPID0—Capability Identifier (D0:F0) .................................................94
5
MCHBAR Registers ..........................................................................................................95
5.1 MCHBAR Register Details ...................................................................................96
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
C0DRB0—Channel A DRAM Rank Boundary Address 0 ....................96
C0DRB1—Channel A DRAM Rank Boundary Address 1 ....................98
C0DRB2—Channel A DRAM Rank Boundary Address 2 ....................98
C0DRB3—Channel A DRAM Rank Boundary Address 3 ....................98
C0DRA0—Channel A DRAM Rank 0,1 Attribute .................................99
C0DRA2—Channel A DRAM Rank 2,3 Attribute .................................99
C0DCLKDIS—Channel A DRAM Clock Disable ................................100
C0BNKARC—Channel A DRAM Bank Architecture ..........................101
C0DRT1—Channel A DRAM Timing Register ...................................102
5.1.10 C0DRC0—Channel A DRAM Controller Mode 0 ...............................104
5.1.11 C1DRB0—Channel B DRAM Rank Boundary Address 0 ..................106
4
Datasheet
INTEL [ INTEL ]
