Introduction
R
configuration space. Host-initiated memory cycles are decoded to PCI Express, DMI, or system
memory. PCI Express device accesses to non-cacheable system memory are not snooped on the
host bus. Memory accesses initiated from PCI Express using PCI semantics and from DMI to
system memory will be snooped on the host bus.
1.3.2
System Memory Interface
The (G)MCH integrates a system memory DDR/DDR2 controller with two, 64-bit wide interfaces
(82910GL, 82915PL, and 82915GL supports DDR only). Only Double Data Rate (DDR/DDR2)
memory is supported; consequently, the buffers support only SSTL_2/1.8 V signal interfaces. The
memory controller interface is fully configurable through a set of control registers. Features of the
(G)MCH memory controller include:
• The (G)MCH System Memory Controller directly supports one or two channels of memory
(each channel consisting of 64 data lines).
• Supports two memory addressing organization options:
⎯ The memory channels are asymmetric: "Stacked" channels are assigned addresses
serially. Channel B addresses are assigned after all Channel A addresses.
⎯ The memory channels are interleaved: Addresses are ping-ponged between the channels
after each cache line (64-B boundary).
• Available bandwidth up to:
⎯ 3.2 GB/s (DDR/DDR2 400) for single-channel mode
⎯ 6.4 GB/s in dual-channel interleaved mode assuming DDR or DDR2 400 MHz.
⎯ 8.5 GB/s in dual-channel interleaved mode assuming DDR2 533 MHz.
• Supports DDR memory DIMM frequencies of 333 MHz and 400 MHz or DDR2 memory
DIMM frequencies of 400 MHz and 533 MHz. All DIMMs in a system must be of the same
type (e.g., all DDR or all DDR2, not mixed). The speed used in all channels is the speed of
the slowest DIMM in the system.
• 82910GL supports DDR memory only, DIMM frequencies of 333 MHz and 400 MHz, dual
channel mode, 1-DIMM maximum per channel.
• I/O Voltage of 2.6 V for DDR, and 1.8 V for DDR2.
• Supports non-ECC memory only.
• Supports 256-Mb, 512-Mb and 1-Gb DDR/DDR2 technologies
• Supports only x8, x16, DDR/DDR2 devices with four banks and also supports eight bank,
1-Gbit DDR2 devices.
• Supports opportunistic refresh
• In dual channel mode the (G)MCH supports 64 simultaneously open pages (four ranks of
eight bank devices* 2 channels)
• Supports Partial Writes to memory using Data Mask (DM) signals.
• Supports page sizes of 4 KB, 8 KB and 16 KB.
• Supports a burst length of 8 for single-channel and dual-channel interleaved and asymmetric
operating modes.
• Supports unbuffered DIMMs.
• SPD (Serial Presence Detect) scheme for DIMM detection support
• Suspend-to-RAM support using CKE
• Supports configurations defined in the JEDEC DDR/DDR2 DIMM specification only
Datasheet
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INTEL [ INTEL ]
