Introduction
R
Term
Description
The Memory Controller Hub (MCH) component contains the processor interface and
DRAM controller; however, it does not contain an internal graphics device like the
GMCH. It may also contain an x16 PCI Express port (typically the external graphics
interface). It communicates with the I/O controller hub (ICH6*) and other I/O controller
hubs over the DMI interconnect. Throughout this document the term MCH refers to the
82915P and 82915PL MCH. Note: (G)MCH is used when referring to both GMCH and
MCH components.
MCH
Message Signaled Interrupt. A transaction initiated outside the host, conveying interrupt
information to the receiving agent through the same path that normally carries read and
write commands.
MSI
Third Generation Input Output (PCI Express) Graphics Attach called PCI Express
Graphics. A high-speed serial interface whose configuration is software compatible with
the existing PCI specifications. The specific PCI Express implementation intended for
connecting the GMCH to an external graphics controller is a x16 link and replaces AGP.
PCI Express*
Primary PCI
The physical PCI bus that is driven directly by the ICH6 component. Communication
between Primary PCI and the GMCH occurs over DMI. Note that the Primary PCI bus is
not PCI Bus 0 from a configuration standpoint.
System Control Interrupt. SCI is used in ACPI protocol.
SCI
Serial Digital Video Out (SDVO). Digital display channel that serially transmits digital
display data to an external SDVO device. The SDVO device accepts this serialized
format and then translates the data into the appropriate display format (i.e., TMDS,
LVDS, TV-Out). This interface is not electrically compatible with the previous digital
display channel - DVO. For the Intel® 82915G GMCH, The SDVO interface is
multiplexed on a portion of the x16 graphics PCI Express interface.
SDVO
Third party codec that uses SDVO as an input. An SDVO device may have a variety of
output formats including: DVI, LVDS, HDMI, TV-Out, etc.
SDVO Device
An indication that an unrecoverable error has occurred on an I/O bus.
SERR
SMI
System Management Interrupt. SMI is used to indicate any of several system conditions
(such as thermal sensor events, throttling activated, access to System Management
RAM, chassis open, or other system state related activity).
A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four x16
SDRAM devices in parallel, ignoring ECC. These devices are usually, but not always,
mounted on a single side of a DIMM.
Rank
Transition Minimized Differential Signaling. Signaling interface from Silicon Image that
is used in DVI and HDMI.
TMDS
TOLM
Top Of Low Memory. The highest address below 4 GB for which a processor-initiated
memory read or write transaction will create a corresponding cycle to DRAM on the
memory interface.
Voltage Controlled Oscillator.
VCO
UMA
Unified Memory Architecture. UMA describes an IGD using system memory for its
frame buffers.
Datasheet
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INTEL [ INTEL ]
