Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.49
VC0RCAP—VC0 Resource Capability (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
110h
00000000h
RO
Size:
32 bits
Bit
Access &
Default
Description
31:16
15
Reserved
Reject Snoop Transactions
RO
0b
0 = Transactions with or without the No Snoop bit set within the TLP header are
allowed on this VC.
1 = Any transaction without the No Snoop bit set within the TLP header will be
rejected as an Unsupported Request.
14:0
Reserved
8.1.50
VC0RCTL—VC0 Resource Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
114h
8000007Fh
RO, R/W
32 bits
Size:
This register controls the resources associated with PCI Express Virtual Channel 0.
Bit
Access &
Default
Description
31
RO
1b
VC0 Enable: For VC0, this is hardwired to 1 and read only as VC0 can never be
disabled.
30:27
26:24
Reserved
RO
VC0 ID: This field assigns a VC ID to the VC resource. For VC0 this is hardwired
000b
to 0 and read only.
23:8
7:1
Reserved
R/W
7Fh
TC/VC0 Map: This field indicates the TCs (Traffic Classes) that are mapped to
the VC resource. Bit locations within this field correspond to TC values. For
example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When
more than one bit in this field is set, it indicates that multiple TCs are mapped to
the VC resource. In order to remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or outstanding transactions with
the TC labels are targeted at the given Link.
0
RO
1b
TC0/VC0 Map: Traffic Class 0 is always routed to VC0.
Datasheet
165
INTEL [ INTEL ]
