Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
0F–17h
18h
—
PBUSN1
SBUSN1
SUBUSN1
—
Reserved
—
00h
—
RO
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Reserved
19h
00h
RO
1Ah
00h
R/W
—
1Bh
—
1Ch
IOBASE1
IOLIMIT1
SSTS1
I/O Base Address
F0h
00h
RO
1Dh
I/O Limit Address
R/W
RO, R/W/C
R/W
R/W
RO, R/W
RO, R/W
—
1Eh–1Fh
20–21h
22–23h
24–25h
26–27h
28–33h
34h
Secondary Status
00h
MBASE1
MLIMIT1
PMBASE1
PMLIMIT1
—
Memory Base Address
Memory Limit Address
Prefetchable Memory Base Address
Prefetchable Memory Limit Address
Reserved
FFF0h
0000h
FFF0h
0000h
—
CAPPTR1
—
Capabilities Pointer
Reserved
88h
RO
35–3Bh
3Ch
—
—
INTRLINE1
INTRPIN1
BCTRL1
—
Interrupt Line
00h
R/W
RO
3Dh
Interrupt Pin
00h
3E–3Fh
40–7Fh
80–83h
Bridge Control
0000h
—
RO, R/W
—
Reserved
PM_CAPID1
Power Management Capabilities
19029001h
or
RO
1902A001h
84–87h
88–8Bh
PM_CS1
Power Management Control/Status
00000000h
RO, R/W/S
RO
SS_CAPID
Subsystem ID and Vendor ID Capabilities
0000800D
h
8C–8Fh
90–91h
92–93h
94–97h
98–99h
9A–9Fh
A0–A1h
A2–A3h
A4–A7h
A8–A9h
AA–ABh
AC–AFh
B0–B1h
SS
MSI_CAPID
MC
Subsystem ID and Subsystem Vendor ID
Message Signaled Interrupts Capability ID
Message Control
00008086h
A005h
RO
RO
0000h
RO, R/W
RO, R/W
R/W
MA
Message Address
00000000h
0000h
MD
Message Data
—
Reserved
—
—
PEG_CAPL
PEG_CAP
DCAP
DCTL
PCI Express* Capability List
PCI Express Capabilities
Device Capabilities
Device Control
0010h
RO
0141h
RO
00000000h
0000h
RO
R/W
DSTS
LCAP
Device Status
0000h
RO
Link Capabilities
02012E01h
0000h
R/WO
RO, R/W
LCTL
Link Control
126
Datasheet
INTEL [ INTEL ]
