DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
7.1.6
DMIVC0RCTL0—DMI VC0 Resource Control
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
014h
8000007Fh
R/W, RO
32 bits
Size:
This register controls the resources associated with PCI Express Virtual Channel 0.
Bit
Access &
Default
Description
31
RO
1b
Virtual Channel Enable (EN): Enables the VC when set. Disables the VC when
cleared.
30:27
26:24
Reserved
RO
Virtual Channel Identifier (ID): Indicates the ID to use for this virtual channel.
000b
23:20
19:17
Reserved
R/W
0h
Port Arbitration Select (PAS): Indicates which port table is being programmed.
The root complex takes no action on this setting since the arbitration is fixed and
there is no arbitration table.
16
RO
0b
Load Port Arbitration Table (LAT): The root complex does not implement an
arbitration table for this virtual channel.
15:8
7:1
Reserved
R/W
7Fh
Transaction Class / Virtual Channel Map (TVM): This field indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
0
Reserved
Datasheet
119
INTEL [ INTEL ]
