82551IT — Networking Silicon
Table 14. PCI Status Register Bits
Bits
Name
Description
This bit indicates whether a parity error has been detected. This bit is set to
1b when the following three conditions are met:
1. The bus agent asserted PERR# itself or observed PERR# asserted.
2. The agent setting the bit acted as the bus master for the operation in
which the error occurred.
24
Parity Error Detected
3. The Parity Error Response bit in the command register (bit 6) is set.
In the 82551IT, the initial value of the Parity Error Detected bit is 0b. This
bit is set until cleared by writing a 1b.
This bit indicates a device’s ability to accept fast back-to-back transactions
when the transactions are not to the same agent. A value of 0b disables
fast back-to-back ability. A value of 1b enables fast back-to-back ability. In
the 82551IT, this bit is read only and is set to 1b.
23
Fast Back-to-Back
This bit indicates whether the 82551IT implements a list of new capabilities
such as PCI Power Management. A value of 0b means that this function
does not implement the Capabilities List. If this bit is set to 1b, the Cap_Ptr
register provides an offset into the 82551IT PCI Configuration space
pointing to the location of the first item in the Capabilities List. This bit is set
only if the power management bit in the EEPROM is set.
20
Capabilities List
Reserved
19:16
These bits are reserved and should be set to 0b.
44
Datasheet
INTEL [ INTEL ]
