82551IT — Networking Silicon
4.5
PHY Signals
Table 8. PHY Signals
Symbol
Type
Name and Function
Crystal Input One. X1 and X2 can be driven by an external 25 MHz
crystal. Otherwise, X1 may be driven by an external 3.3 V metal-oxide
semiconductor (MOS) level 25 MHz oscillator when X2 is left floating.
X1
X2
AI
Crystal Input Two. X1 and X2 can be driven by an external 25 MHz
crystal. Otherwise, X1 may be driven by an external 3.3 V MOS level
25 MHz oscillator when X2 is left floating.
AO
AO
Analog Twisted Pair Ethernet Transmit Differential Pair. These
pins transmit the serial bit stream for transmission on the Unshielded
Twisted Pair (UTP) cable. The current-driven differential driver can be
two-level (10BASE-T) or three-level (100BASE-TX) signals depending
on the mode of operation. These signals interface directly with an
isolation transformer.
TDP
TDN
Analog Twisted Pair Ethernet Receive Differential Pair. Thesepins
receive the serial bit stream from the isolation transformer. The bit
stream can be two-level (10BASE-T) or three-level (100BASE-TX)
signals depending on the mode of operation.
RDP
RDN
AI
Activity LED. The Activity LED pin indicates either transmit or receive
activity. When activity is present, the activity LED is on (ACTLED#
active low); when no activity is present, the activity LED is off.
ACTLED#
LILED#
OUT
OUT
Link Integrity LED. The Link Integrity LED pin indicates link integrity.
If the link is valid in either 10 or 100 Mbps, the LED is on (LILED#
active low); if link is invalid, the LED is off.
Speed LED. The Speed LED pin indicates the speed. The speed LED
will be on at 100 Mbps (SPDLED# active low) and off at 10 Mbps.
SPDLED#
RBIAS100
RBIAS10
OUT
B
Reference Bias Resistor (100 Mbps). This pin should be connected
to a pull-down resistor.a
Reference Bias Resistor (10 Mbps). This pin should be connected
B
to a pull-down resistor.a
Voltage Reference. This pin is connected to a 1.25 V ± 1% external
voltage reference generator. To use the internal voltage reference
source, this pin should be left floating. Under normal circumstances,
the internal voltage reference should be used and this pin would be left
open.
VREF
B
a. Based on some board designs, RBIAS100 and RBIAS10 values may need to be increased/decreased to com-
pensate for high/low MDI transmit amplitude. See the 82562EZ(EX)/82551ER(IT) & 82541ER Combined Foot-
print LOM Design Guide for more information.
12
Datasheet
INTEL [ INTEL ]
