Networking Silicon — 82551IT
Table 6. Local Memory Interface Signals
Symbol
FLA6:2
Type
OUT
Name and Function
Flash Address 6:2. These pins are used as Flash address outputs.
These pins should be left floating if the Flash is not used.
Flash Address 1/Auxiliary Power. This multiplexed pin acts as the
Flash Address 1 output signal during nominal operation. When the
power-on reset of the 82551IT is active (low), it acts as the power
supply indicator. If the 82551IT is fed by auxiliary power, it should be
connected to VCC through a pull-up resistor (3.3 K). Otherwise, this
pin should be left floating.
FLA1/
AUXPWR
TS
TS
Flash Address 0/PCI Mode. This multiplexed pin acts as the Flash
Address 0 output signal during nominal operation. When power-on
reset of the 82551IT is active (low), it acts as the input system type.
For PCI systems that do not use Flash, this pin should be left floating.
FLA0/
PCIMODE#
EEPROM Chip Select. The EEPROM Chip Select signal is used to
assert chip select to the serial EEPROM.
EECS
OUT
OUT
Flash Chip Select. The Flash Chip Select pin provides an active low
Flash chip select signal. This pin should be left floating if Flash is not
used.
FLCS#
Flash Output Enable. This pin provides an active low output enable
control (read) to the Flash memory. This pin should be left floating if
Flash is not used.
FLOE#
FLWE#
OUT
OUT
Flash Write Enable. This pin provides an active low write enable
control to the Flash memory. This pin should be left floating if Flash is
not used.
4.4
Test Port Signals
Table 7. Test Port Signals
Symbol
Type
Name and Function
Test Port. If this input pin is high, the 82551IT will enable the test port.
During nominal operation this pin should be connected to a 1K pull-
down resistor.
TEST
IN
TCK
TI
IN
IN
Test Port Clock. This pin is used for the Test Port Clock signal.
Test Port Data Input. This pin is used for the Test Port Data Input
signal.
Test Port Execute Enable. This pin is used for the Test Port Execute
Enable signal.
TEXEC
TO
IN
Test Port Data Output. This pin is used for the Test Port Data Output
signal.
OUT
Note: These test port signals are not JTAG compatible. As a result, a BSDL file is not required.
Datasheet
11
INTEL [ INTEL ]
