82551IT — Networking Silicon
4.2
PCI Bus Interface Signals
4.2.1
Address and Data Signals
Table 3. Address and Data Signals
Symbol
Type
Name and Function
Address and Data. The address and data lines are multiplexed on
the same PCI pins. A bus transaction consists of an address phase
followed by one or more data phases. During the address phase, the
address and data lines contain the 32-bit physical address. For I/O,
this is a byte address; for configuration and memory, it is a Dword
address. The 82551IT uses little-endian byte ordering (in other words,
AD[31:24] contain the most significant byte and AD[7:0] contain the
least significant byte). During the data phases, the address and data
lines contain data.
AD[31:0]
TS
Command and Byte Enable. The bus command and byte enable
signals are multiplexed on the same PCI pins. During the address
phase, the C/BE# lines define the bus command. During the data
phase, the C/BE# lines are used as Byte Enables. The Byte Enables
are valid for the entire data phase and determine which byte lanes
carry meaningful data.
C/BE#[3:0]
TS
TS
Parity. Parity is even across AD[31:0] and C/BE#[3:0] lines. It is stable
and valid one clock after the address phase. For data phases, PAR is
stable and valid one clock after either IRDY# is asserted on a write
transaction or TRDY# is asserted on a read transaction.Once PAR is
valid, it remains valid until one clock after the completion of the current
data phase. The master drives PAR for address and write data
phases; and the target, for read data phases.
PAR
4.2.2
Interface Control Signals
Table 4. Interface Control Signals
Symbol
Type
Name and Function
Cycle Frame. The cycle frame signal is driven by the current master
to indicate the beginning and duration of a transaction. FRAME# is
asserted to indicate the start of a transaction and de-asserted during
the final data phase.
FRAME#
STS
Initiator Ready. The initiator ready signal indicates the bus master’s
ability to complete the current data phase and is used in conjunction
with the target ready (TRDY#) signal. A data phase is completed on
any clock cycle where both IRDY# and TRDY# are sampled asserted
(low) simultaneously.
IRDY#
TRDY#
STOP#
STS
STS
STS
Target Ready. The target ready signal indicates the selected device’s
ability to complete the current data phase and is used in conjunction
with the initiator ready (IRDY#) signal. A data phase is completed on
any clock cycle where both IRDY# and TRDY# are sampled asserted
(low) simultaneously.
Stop. The stop signal is driven by the target to indicate to the initiator
that it wishes to stop the current transaction. As a bus slave, STOP# is
driven by the 82551IT to inform the bus master to stop the current
transaction. As a bus master, STOP# is received by the 82551IT to
stop the current transaction.
8
Datasheet
INTEL [ INTEL ]
