80C186EC/188EC, 80L186EC/188EC
Relative Timings (80C186EC-25/20/13, 80L186EC-16/13)
NOTES:
1. Assumes equal loading on both pins.
2. Can be extended using wait states.
3. Interrupt resolution time is the delay between an unmasked interrupt request going active and the interrupt output of the
8259A module going active. This is not directly measureable by the user. For interrupt pin INT7 the delay from an active
signal to an active input to the CPU would actually be twice the T
modules.
value since the signal must pass through two 8259A
IRES
4. See INTA Cycle Waveforms for definition.
5. To guarantee interrupt is not spurious.
Serial Port Mode 0 Timings (80C186EC-25/20/13, 80L186EC-16/13)
Symbol
Parameter
Min
Max
Unit
Notes
RELATIVE TIMINGS
a
T
T
T
T
T
T
TXD Clock Period
TXD Clock Low to Clock High (N 1)
T (n
1)
ns
ns
ns
ns
ns
ns
1, 2
1
XLXL
XLXH
XLXH
XHXL
XHXL
QVXH
l
b
a
35
2T
T
35
2T
T
e
l
b
a
35
TXD Clock Low to Clock High (N
1)
35
1
b
b
b
a
35
TXD Clock High to Clock Low (N 1)
(n
(n
1) T
35
35
(n
1) T
a
1, 2
1
e
b
TXD Clock High to Clock Low (N
1)
T
35
T
35
b
b
35
35
35
RXD Output Data Setup to TXD
l
Clock High (N 1)
1)T
1, 2
b
T
T
T
T
T
T
RXD Output Data Setup to TXD
e
T
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
QVXH
XHQX
XHQX
XHQZ
DVXH
XHDX
Clock High (N
1)
b
RXD Output Data Hold after TXD
l
Clock High (N 1)
2T
T
b
RXD Output Data Hold after TXD
e
Clock High (N
1)
a
20
RXD Output Data Float after Last
TXD Clock High
T
a
RXD Input Data Setup to TXD
Clock High
T
20
RXD Input Data Setup after TXD
Clock High
0
NOTES:
1. See Figure 13 for Waveforms.
2. n is the value in the BxCMP register ignoring the ICLK bit.
36
INTEL [ INTEL ]
