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80C188EC25 参数 Datasheet PDF下载

80C188EC25图片预览
型号: 80C188EC25
PDF下载: 下载PDF文件 查看货源
内容描述: 16位高集成嵌入式处理器 [16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS]
分类和应用:
文件页数/大小: 57 页 / 787 K
品牌: INTEL [ INTEL ]
 浏览型号80C188EC25的Datasheet PDF文件第28页浏览型号80C188EC25的Datasheet PDF文件第29页浏览型号80C188EC25的Datasheet PDF文件第30页浏览型号80C188EC25的Datasheet PDF文件第31页浏览型号80C188EC25的Datasheet PDF文件第33页浏览型号80C188EC25的Datasheet PDF文件第34页浏览型号80C188EC25的Datasheet PDF文件第35页浏览型号80C188EC25的Datasheet PDF文件第36页  
80C186EC/188EC, 80L186EC/188EC  
AC SPECIFICATIONS  
AC CharacteristicsÐ80C186EC-20/80C186EC-13  
Symbol  
Parameter  
Min  
Max  
Min  
Max  
Unit Notes  
INPUT CLOCK  
20 MHz  
13 MHz  
TF  
TC  
TCH  
TCL  
TCR  
TCF  
CLKIN Frequency  
CLKIN Period  
CLKIN High Time  
CLKIN Low Time  
CLKIN Rise Time  
CLKIN Fall Time  
0
25  
10  
10  
1
40  
%
%
%
10  
10  
0
38.5  
12  
12  
1
26  
%
%
%
10  
10  
MHz  
ns  
ns  
ns  
ns  
1
1
1, 2  
1, 2  
1, 3  
1, 3  
1
1
ns  
OUTPUT CLOCK  
T
T
T
T
T
T
CLKIN to CLKOUT Delay  
CLKOUT Period  
CLKOUT High Time  
CLKOUT Low Time  
CLKOUT Rise Time  
CLKOUT Fall Time  
0
17  
0
23  
ns  
ns  
ns  
ns  
ns  
ns  
1, 4  
1
1
1
1, 5  
1, 5  
CD  
2 * TC  
2 * TC  
b
a
a
b
a
a
(T/2) 5 (T/2)  
b
(T/2) 5 (T/2)  
5 (T/2) 5 (T/2)  
b
5 (T/2) 5 (T/2)  
5
5
PH  
PL  
PR  
PF  
1
1
6
6
1
1
6
6
OUTPUT DELAYS  
T
T
T
T
T
T
ALE, S2:0, DEN, DT/R,  
BHE (RFSH), LOCK, A19:16  
3
3
3
3
0
0
20  
23  
20  
23  
25  
25  
3
3
3
3
0
0
25  
30  
25  
30  
30  
30  
ns 1, 4, 6, 7  
ns 1, 4, 6, 8  
ns 1, 4, 6  
ns 1, 4, 6  
CHOV1  
CHOV2  
CLOV1  
CLOV2  
CHOF  
GCS7:0, LCS, UCS,  
RD, WR, NCS, WDTOUT  
BHE (RFSH), DEN, LOCK, RESOUT,  
HLDA, T0OUT, T1OUT  
RD, WR, GSC7:0, LCS, UCS, AD15:0  
(AD7:0, A15:8), NCS, INTA, S2:0, A19:16  
RD, WR, BHE (RFSH), DT/R, LOCK,  
S2:0, A19:16  
ns  
ns  
1
1
DEN, AD15:0 (AD7:0, A15:8)  
CLOF  
INPUT REQUIREMENTS  
T
TEST, NMI, T1IN, T0IN, READY,  
CTS1:0, BCLK1:0, P3.4, P3.5  
10  
3
10  
3
ns  
ns  
1, 9  
1, 9  
CHIS  
T
TEST, NMI, T1IN, T0IN, READY,  
CTS1:0, BCLK1:0, P3.4, P3.5  
CHIH  
T
T
T
T
AD15:0 (AD7:0), READY  
10  
3
10  
3
ns  
ns  
ns  
ns  
1, 10  
1, 10  
1, 9  
CLIS  
CLIH  
CLIS  
CLIH  
AD15:0 (AD7:0), READY  
HOLD, RESIN, PEREQ, ERROR, DRQ3:0  
HOLD, RESIN, REREQ, ERROR, DRQ3:0  
10  
3
10  
3
1, 9  
NOTES:  
1. See AC Timing Waveforms, for waveforms and definition.  
2. Measure at V for high time, V for low time.  
IH IL  
3. Only required to guarantee I . Maximum limits are bounded by T , T  
C
and T  
.
CL  
CC  
CH  
4. Specified for a 50 pF load, see Figure 14 for capacitive derating information.  
5. Specified for a 50 pF load, see Figure 15 for rise and fall times outside 50 pF.  
6. See Figure 15 for rise and fall times.  
7. T  
8. T  
applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.  
applies to RD and WR only after a HOLD release.  
CHOV1  
CHOV2  
9. Setup and Hold are required to guarantee recognition.  
10. Setup and Hold are required for proper operation.  
32  
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