80C186EC/188EC, 80L186EC/188EC
PDTMR Pin Delay Calculation
I
CC
versus Frequency and Voltage
The I consumed by the processor is composed of
CC
two components:
The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown Mode. A delay is
required only when using the on chip oscillator to
allow the crystal or resonator circuit to stabilize.
1. I ÐThe quiescent current that represents inter-
PD
nal device leakage. Measured with all inputs at
either V
or ground and no clock applied.
CC
2. I
ÐThe switching current used to charge and
CCS
NOTE:
discharge internal parasitic capacitance when
changing logic levels. I is related to both the
frequency of operation and the device supply
The PDTMR pin function does not apply when
RESIN is asserted (i.e. a device reset while in Pow-
erdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabilized.
CCS
voltage (V ). I
is given by the formula:
CC CCS
2
e
e
V
Power
.
V * I
* C
* f
DEV
To calculate the value of capacitor to use to provide
a desired delay, use the equation:
e
. . I
V * C
* f
CCS
DEV
c
e
C
Where:
440
t
(5V, 25 C)
§
PD
e
V
C
f
Supply Voltage (V
)
CC
Where:
e
Device Capacitance
DEV
e
e
Operating Frequency
t
desired delay in seconds
e
C
capacitive load on PDTMR in microfarads
PD
Measuring C
would be difficult. Instead, C
on a device like the 80C186EC
is calculated using
values measured at
PD
Example. For a delay of 300 ms, a capacitor value of
PD
b
e
0.132 mF is required.
6
e
c
c
the above formula with I
CC
known V and frequency. Using the C value, the
C
440 (300 10
PD
Round up to a standard (available) capacitor value.
CC PD
user can calculate I at any voltage and frequency
CC
within the specified operating range.
NOTE:
The above equation applies to delay time longer
than 10 ms and will compute the TYPICAL capaci-
tance needed to achieve the desired delay. A delay
Example. Calculate typical I at 14 MHz, 5.2V V
CC
.
CC
e
e
e
a
I
I
I
a
b
variance of
temperature, voltage, and device process ex-
tremes. In general, higher V and/or lower tem-
50% to
25% can occur due to
CC
PD
0.1 mA
56.2 mA
CCS
a
5.2V * 0.77 * 14 MHz
CC
peratures will decrease delay time, while lower V
CC
and/or higher temperature will increase delay time.
Parameter
CPD
CPD (Idle Mode)
Typical
0.77
Max
1.37
0.96
Units
Notes
1, 2
mA/V*MHz
mA/V*MHz
0.55
1, 2
NOTES:
1. Maximum C is measured at 40 C with all outputs loaded as specified in the AC test conditions and the device in reset
b
§
PD
(or Idle Mode). Due to tester limitations, CLKOUT and OSCOUT also have 50 pF loads that increase I
by V*C*F.
CC
2. Typical C is calculated at 25 C assuming no loads on CLKOUT or OSCOUT and the device in reset (or Idle Mode).
§
PD
29
INTEL [ INTEL ]
