A
80960JD
Table 9. 132-Lead PQFP Pinout — In Pin Order
Pin
1
Signal
Pin
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Signal
BLAST
D/C
Pin
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
Signal
NC
Pin
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
Signal
AD8
TRST
TCK
2
AD26
AD7
3
TMS
ADS
AD25
AD6
4
HOLD
XINT0
XINT1
XINT2
XINT3
VCC (I/O)
VSS (I/O)
XINT4
XINT5
XINT6
XINT7
NMI
W/R
AD24
AD5
5
VSS (Core)
VCC (Core)
VSS (I/O)
VCC (I/O)
DT/R
VSS (I/O)
VCC (I/O)
VSS (Core)
VCC (Core)
AD23
AD4
6
VCC (I/O)
VSS (I/O)
AD3
7
8
9
AD2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
DEN
AD22
AD1
HOLDA
ALE
AD21
AD0
AD20
VCC (I/O)
VSS (I/O)
VCC (Core)
VSS (Core)
VCC (Core)
VSS (Core)
CLKIN
VSS (CLK)
VCCPLL
VCC (CLK)
NC
VSS (Core)
VCC (Core)
VSS (I/O)
VCC (I/O)
LOCK/ONCE
BSTAT
VSS (I/O)
VCC (I/O)
AD19
VCC (Core)
VSS (Core)
NC
AD18
AD17
AD16
NC
BE0
VSS (I/O)
VCC (I/O)
AD15
NC
BE1
NC
BE2
NC
BE3
AD14
FAIL
VSS (I/O)
VCC (I/O)
VSS (Core)
VCC (Core)
AD31
AD13
NC
ALE
AD12
VCC (Core)
VSS (Core)
RESET
NC
TDO
VSS (Core)
VCC (Core)
VSS (I/O)
VCC (I/O)
AD11
VCC (I/O)
VSS (I/O)
WIDTH/HLTD1
VCC (Core)
VSS (Core)
WIDTH/HLTD0
A2
AD30
NC
AD29
STEST
VCC (I/O)
TDI
AD28
AD10
VSS (I/O)
VCC (I/O)
AD27
VSS (I/O)
VCC (I/O)
AD9
VSS (I/O)
RDYRCV
A3
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
19
PRELIMINARY
INTEL [ INTEL ]
